![](http://datasheet.mmic.net.cn/260000/PIC18F23K20_datasheet_15942918/PIC18F23K20_79.png)
2007 Microchip Technology Inc.
Advance Information
DS41303B-page 77
PIC18F2XK20/4XK20
TABLE 5-2:
REGISTER FILE SUMMARY (PIC18F2XK20/4XK20)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on page:
TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000
57, 64
TOSH
Top-of-Stack, High Byte (TOS<15:8>)
0000 0000
57, 64
TOSL
Top-of-Stack, Low Byte (TOS<7:0>)
0000 0000
57, 64
STKPTR
STKFUL
STKUNF
—
SP4
SP3
SP2
SP1
SP0
00-0 0000
57, 65
PCLATU
—
—
—
Holding Register for PC<20:16>
---0 0000
57, 64
PCLATH
Holding Register for PC<15:8>
0000 0000
57, 64
PCL
PC, Low Byte (PC<7:0>)
0000 0000
57, 64
TBLPTRU
—
—
bit 21
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
--00 0000
57, 90
TBLPTRH
Program Memory Table Pointer, High Byte (TBLPTR<15:8>)
0000 0000
57, 90
TBLPTRL
Program Memory Table Pointer, Low Byte (TBLPTR<7:0>)
0000 0000
57, 90
TABLAT
Program Memory Table Latch
0000 0000
57, 90
PRODH
Product Register, High Byte
xxxx xxxx
57, 101
PRODL
Product Register, Low Byte
xxxx xxxx
57, 101
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
57, 105
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
—
TMR0IP
—
RBIP
1111 -1-1
57, 106
INTCON3
INT2IP
INT1IP
—
INT2IE
INT1IE
—
INT2IF
INT1IF
11-0 0-00
57, 107
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
57, 82
POSTINC0
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
57, 82
POSTDEC0
Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
N/A
57, 82
PREINC0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
57, 82
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
N/A
57, 82
FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0, High Byte
---- 0000
57, 82
FSR0L
Indirect Data Memory Address Pointer 0, Low Byte
xxxx xxxx
57, 82
WREG
Working Register
xxxx xxxx
57
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
N/A
57, 82
POSTINC1
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
57, 82
POSTDEC1
Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
57, 82
PREINC1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
57, 82
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A
57, 82
FSR1H
—
—
—
—
Indirect Data Memory Address Pointer 1, High Byte
---- 0000
58, 82
FSR1L
Indirect Data Memory Address Pointer 1, Low Byte
xxxx xxxx
58, 82
BSR
—
—
—
—
Bank Select Register
---- 0000
58, 69
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
58, 82
POSTINC2
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
58, 82
POSTDEC2
Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
N/A
58, 82
PREINC2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
58, 82
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A
58, 82
FSR2H
—
—
—
—
Indirect Data Memory Address Pointer 2, High Byte
---- 0000
58, 82
FSR2L
Indirect Data Memory Address Pointer 2, Low Byte
xxxx xxxx
58, 82
STATUS
—
—
—
N
OV
Z
DC
C
---x xxxx
58, 80
Legend:
Note
x
= unknown,
u
= unchanged,
—
= unimplemented,
q
= value depends on condition
The SBOREN bit is only available when the BOREN<1:0> Configuration bits =
01
; otherwise it is disabled and reads as ‘
0
’. See
Section 4.4 “Brown-out Reset (BOR)”
.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘
0
’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘
-
’.
The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as ‘
0
’. See
Section 2.6.2 “PLL in
HFINTOSC Modes”
.
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit =
0
). Otherwise, RE3 reads as ‘
0
’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘
0
’.
All bits of the ANSELH register initialize to ‘
0
’ if the PBADEN bit of CONFIG3H is ‘
0
’.
1:
2:
3:
4:
5:
6: