
PIC18F2XK20/4XK20
DS41303B-page 136
Advance Information
2007 Microchip Technology Inc.
FIGURE 10-3:
PARALLEL SLAVE PORT WRITE WAVEFORMS
FIGURE 10-4:
PARALLEL SLAVE PORT READ WAVEFORMS
TABLE 10-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
PORTD
LATD
TRISD
PORTE
LATE
TRISE
SLRCON
INTCON
PIR1
PIE1
IPR1
ANSEL
Legend:
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
60
60
60
60
60
60
61
57
60
60
60
60
PORTD Data Latch Register (Read and Write to Data Latch)
PORTD Data Direction Control Register
—
—
—
—
—
—
IBF
OBF
IBOV
—
—
—
GIE/GIEH PEIE/GIEL
TMR0IF
PSPIF
ADIF
RCIF
PSPIE
ADIE
RCIE
PSPIP
ADIP
RCIP
ANS7
ANS6
ANS5
— = unimplemented, read as ‘
0
’. Shaded cells are not used by the Parallel Slave Port.
—
—
RE3
—
—
SLRD
RBIE
SSPIF
SSPIE
SSPIP
ANS3
RE2
RE1
RE0
LATE Data Output bits
TRISE2
SLRC
TMR0IF
CCP1IF
CCP1IE
CCP1IP
ANS2
PSPMODE
SLRE
INT0IE
TXIF
TXIE
TXIP
ANS4
TRISE1
SLRB
INT0IF
TMR2IF
TMR2IE
TMR2IP
ANS1
TRISE0
SLRA
RBIF
TMR1IF
TMR1IE
TMR1IP
ANS0
Q1
Q2
Q3
Q4
CS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
WR
RD
IBF
OBF
PSPIF
PORTD<7:0>
Q1
Q2
Q3
Q4
CS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
WR
IBF
PSPIF
RD
OBF
PORTD<7:0>