參數(shù)資料
型號: PIC18F45J50-I/PT
廠商: Microchip Technology
文件頁數(shù): 64/164頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 32K 2V 44-TQFP
產(chǎn)品培訓(xùn)模塊: XLP Deep Sleep Mode
PIC18 J Series MCU Overview
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 160
系列: PIC® XLP™ 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 48MHz
連通性: I²C,SPI,UART/USART,USB
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
RAM 容量: 3.8K x 8
電壓 - 電源 (Vcc/Vdd): 2.15 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 13x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 657 (CN2011-ZH PDF)
配用: AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
PIC18F46J50 FAMILY
DS39931D-page 156
2011 Microchip Technology Inc.
REGISTER 10-7:
RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 (BANKED EE7h)
U-0
R/W-1
INTR1R4
INTR1R3
INTR1R2
INTR1R1
INTR1R0
bit 7
bit 0
Legend:
R/W = Readable, Writable bit if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented:
Read as ‘0’
bit 4-0
INTR1R<4:0>:
Assign External Interrupt 1 (INT1) to the Corresponding RPn Pin bits
REGISTER 10-8:
RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2 (BANKED EE8h)
U-0
R/W-1
INTR2R4
INTR2R3
INTR2R2
INTR2R1
INTR2R0
bit 7
bit 0
Legend:
R/W = Readable, Writable bit if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented:
Read as ‘0’
bit 4-0
INTR2R<4:0>:
Assign External Interrupt 2 (INT2) to the Corresponding RPn Pin bits
REGISTER 10-9:
RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 (BANKED EE9h)
U-0
R/W-1
INTR3R4
INTR3R3
INTR3R2
INTR3R1
INTR3R0
bit 7
bit 0
Legend:
R/W = Readable, Writable bit if IOLOCK = 0
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented:
Read as ‘0’
bit 4-0
INTR3R<4:0>:
Assign External Interrupt 3 (INT3) to the Corresponding RPn Pin bits
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