參數資料
型號: PIC18F45J50-I/PT
廠商: Microchip Technology
文件頁數: 125/164頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 32K 2V 44-TQFP
產品培訓模塊: XLP Deep Sleep Mode
PIC18 J Series MCU Overview
8-bit PIC® Microcontroller Portfolio
標準包裝: 160
系列: PIC® XLP™ 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 48MHz
連通性: I²C,SPI,UART/USART,USB
外圍設備: 欠壓檢測/復位,DMA,POR,PWM,WDT
輸入/輸出數: 34
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
RAM 容量: 3.8K x 8
電壓 - 電源 (Vcc/Vdd): 2.15 V ~ 3.6 V
數據轉換器: A/D 13x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
產品目錄頁面: 657 (CN2011-ZH PDF)
配用: AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
2011 Microchip Technology Inc.
DS39931D-page 63
PIC18F46J50 FAMILY
5.0
RESET
The PIC18F46J50 family of devices differentiate
among various kinds of Reset:
a)
Power-on Reset (POR)
b)
MCLR Reset during normal operation
c)
MCLR Reset during power-managed modes
d)
Watchdog
Timer
(WDT)
Reset
(during
execution)
e)
Configuration Mismatch (CM)
f)
Brown-out Reset (BOR)
g)
RESET
Instruction
h)
Stack Full Reset
i)
Stack Underflow Reset
j)
Deep Sleep Reset
This section discusses Resets generated by MCLR,
POR and BOR, and covers the operation of the various
start-up timers.
For information on WDT Resets, see Section 27.2
. For Stack Reset events,
and for Deep Sleep mode, see Section 4.6
Figure 5-1 provides a simplified block diagram of the
on-chip Reset circuit.
5.1
RCON Register
Device Reset events are tracked through the RCON
register (Register 5-1). The lower five bits of the register
indicate that a specific Reset event has occurred. In
most cases, these bits can only be set by the event and
must be cleared by the application after the event. The
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in Section 5.7 “Reset State of
.
FIGURE 5-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR
VDD
WDT
Time-out
VDD Rise
Detect
PWRT
INTRC
POR Pulse
Chip_Reset
Brown-out
Reset(1)
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
Sleep
( )_IDLE
PWRT
S
R
Q
Configuration Word Mismatch
Deep Sleep Reset
Note 1:
The VDD monitoring BOR circuit can be enabled or disabled on “LF” devices based on the DSBOREN
(CONFIG3L<2>) Configuration bit. On “F” devices, the VDD monitoring BOR circuit is only enabled during Deep
Sleep mode by DSBOREN (CONFIG3L<2>).
2:
The VDDCORE monitoring BOR circuit is only implemented on “F” devices. It is always used, except while in Deep
Sleep mode. The VDDCORE monitoring BOR circuit has a trip point threshold of VBOR (Parameter D005).
VDDCORE
Brown-out
Reset(2)
F: 5-Bit Ripple Counter
LF: 11-Bit Ripple Counter
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