參數(shù)資料
型號(hào)： PIC17LC766T-08I/L
廠商： Microchip Technology
文件頁數(shù)： 89/159頁
文件大?。?/td> 0K
描述： IC MCU OTP 16KX16 A/D PWM 84PLCC
標(biāo)準(zhǔn)包裝： 300
系列： PIC® 17C
核心處理器： PIC
芯體尺寸： 8-位
速度： 8MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 66
程序存儲(chǔ)器容量： 32KB（16K x 16）
程序存儲(chǔ)器類型： OTP
RAM 容量： 902 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 84-LCC（J 形引線）
包裝： 帶卷 (TR)
PIC17C7XX
DS30289B-page 34
2000 Microchip Technology Inc.
6.1
Interrupt Status Register (INTSTA)
The Interrupt Status/Control register (INTSTA) contains
the flag and enable bits for non-peripheral interrupts.
The PEIF bit is a read only, bit wise OR of all the periph-
eral flag bits in the PIR registers (Figure 6-4 and
Care should be taken when clearing any of the INTSTA
register enable bits when interrupts are enabled
(GLINTD is clear). If any of the INTSTA flag bits (T0IF,
INTF, T0CKIF, or PEIF) are set in the same instruction
cycle as the corresponding interrupt enable bit is cleared,
the device will vector to the RESET address (0x00).
Prior to disabling any of the INTSTA enable bits, the
GLINTD bit should be set (disabled).
REGISTER 6-1:
INTSTA REGISTER (ADDRESS: 07h, UNBANKED)
Note:
All interrupt flag bits get set by their speci-
fied condition, even if the corresponding
interrupt enable bit is clear (interrupt dis-
abled), or the GLINTD bit is set (all inter-
rupts disabled).
R-0
R/W-0
PEIF
T0CKIF
T0IF
INTF
PEIE
T0CKIE
T0IE
INTE
bit 7
bit 0
bit 7
PEIF: Peripheral Interrupt Flag bit
This bit is the OR of all peripheral interrupt flag bits AND’ed with their corresponding enable bits.
The interrupt logic forces program execution to address (20h) when a peripheral interrupt is
pending.
1
= A peripheral interrupt is pending
0
= No peripheral interrupt is pending
bit 6
T0CKIF: External Interrupt on T0CKI Pin Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to address (18h).
1
= The software specified edge occurred on the RA1/T0CKI pin
0
= The software specified edge did not occur on the RA1/T0CKI pin
bit 5
T0IF: TMR0 Overflow Interrupt Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to address (10h).
1
= TMR0 overflowed
0
= TMR0 did not overflow
bit 4
INTF: External Interrupt on INT Pin Flag bit
This bit is cleared by hardware, when the interrupt logic forces program execution to address (08h).
1
= The software specified edge occurred on the RA0/INT pin
0
= The software specified edge did not occur on the RA0/INT pin
bit 3
PEIE: Peripheral Interrupt Enable bit
This bit acts as a global enable bit for the peripheral interrupts that have their corresponding
enable bits set.
1
= Enable peripheral interrupts
0
= Disable peripheral interrupts
bit 2
T0CKIE: External Interrupt on T0CKI Pin Enable bit
1
= Enable software specified edge interrupt on the RA1/T0CKI pin
0
= Disable interrupt on the RA1/T0CKI pin
bit 1
T0IE: TMR0 Overflow Interrupt Enable bit
1
= Enable TMR0 overflow interrupt
0
= Disable TMR0 overflow interrupt
bit 0
INTE: External Interrupt on RA0/INT Pin Enable bit
1
= Enable software specified edge interrupt on the RA0/INT pin
0
= Disable software specified edge interrupt on the RA0/INT pin
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
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PIC18C242-E/SO 功能描述:8位微控制器 -MCU 16KB 512 RAM 23I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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PIC18C242-I/SO 功能描述:8位微控制器 -MCU 16KB 512 RAM 23I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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