參數(shù)資料
型號： PIC17LC766T-08I/L
廠商： Microchip Technology
文件頁數(shù)： 119/159頁
文件大?。?/td> 0K
描述： IC MCU OTP 16KX16 A/D PWM 84PLCC
標(biāo)準(zhǔn)包裝： 300
系列： PIC® 17C
核心處理器： PIC
芯體尺寸： 8-位
速度： 8MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 66
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： OTP
RAM 容量： 902 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 84-LCC（J 形引線）
包裝： 帶卷 (TR)
2000 Microchip Technology Inc.
DS30289B-page 61
PIC17C7XX
8.1
Table Writes to Internal Memory
A table write operation to internal memory causes a
long write operation. The long write is necessary for
programming the internal EPROM. Instruction execu-
tion is halted while in a long write cycle. The long write
will be terminated by any enabled interrupt. To ensure
that the EPROM location has been well programmed,
a minimum programming time is required (see specifi-
cation #D114). Having only one interrupt enabled to ter-
minate the long write ensures that no unintentional
interrupts will prematurely terminate the long write.
The sequence of events for programming an internal
program memory location should be:
1.
Disable all interrupt sources, except the source
to terminate EPROM program write.
2.
Raise MCLR/VPP pin to the programming
voltage.
3.
Clear the WDT.
4.
Do the table write. The interrupt will terminate
the long write.
5.
Verify the memory location (table read).
8.1.1
TERMINATING LONG WRITES
An interrupt source or RESET are the only events that
terminate a long write operation. Terminating the long
write from an interrupt source requires that the interrupt
enable and flag bits are set. The GLINTD bit only
enables the vectoring to the interrupt address.
If the T0CKI, RA0/INT, or TMR0 interrupt source is
used to terminate the long write, the interrupt flag of the
highest priority enabled interrupt, will terminate the long
write and automatically be cleared.
If a peripheral interrupt source is used to terminate the
long write, the interrupt enable and flag bits must be
set. The interrupt flag will not be automatically cleared
upon the vectoring to the interrupt vector address.
The GLINTD bit determines whether the program will
branch to the interrupt vector when the long write is ter-
minated. If GLINTD is clear, the program will vector, if
GLINTD is set, the program will not vector to the
interrupt address.
TABLE 8-1:
INTERRUPT - TABLE WRITE INTERACTION
Note 1: Programming requirements must be
met. See timing specification in electrical
specifications for the desired device.
Violating these specifications (including
temperature) may result in EPROM
locations that are not fully programmed
and may lose their state over time.
2: If the VPP requirement is not met, the
table write is a 2-cycle write and the pro-
gram memory is unchanged.
Note 1: If an interrupt is pending, the TABLWT is
aborted (a NOP is executed). The highest
priority
pending
interrupt,
from
the
T0CKI, RA0/INT, or TMR0 sources that
is enabled, has its flag cleared.
2: If the interrupt is not being used for the
program write timing, the interrupt
should be disabled. This will ensure that
the interrupt is not lost, nor will it termi-
nate the long write prematurely.
Interrupt
Source
GLINTD
Enable
Bit
Flag
Bit
Action
RA0/INT,
TMR0,
T0CKI
0
1
0
1
0
x
1
Terminate long table write (to internal program memory),
branch to interrupt vector (branch clears flag bit).
None.
Terminate long table write, do not branch to interrupt
vector (flag is automatically cleared).
Peripheral
0
1
0
1
0
x
1
Terminate long table write, branch to interrupt vector.
None.
Terminate long table write, do not branch to interrupt
vector (flag remains set).
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