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2007 Microchip Technology Inc.
Preliminary
DS41291D-page 281
PIC16F882/883/884/886/887
Comparator Output.....................................................83
Enhanced Capture/Compare/PWM (ECCP).............255
Fail-Safe Clock Monitor (FSCM).................................72
Full-Bridge PWM Output...........................................137
Half-Bridge PWM Output ..................................135, 143
I
2
C Master Mode First Start Bit Timing .....................192
I
2
C Master Mode Reception Timing..........................196
I
2
C Master Mode Transmission Timing.....................195
I
2
C Module
Bus Collision
Transmit Timing........................................199
INT Pin Interrupt........................................................218
Internal Oscillator Switch Timing.................................68
Master Mode Transmit Clock Arbitration...................198
PWM Auto-shutdown
Auto-restart Enabled.........................................142
Firmware Restart ..............................................142
PWM Direction Change ............................................138
PWM Direction Change at Near 100% Duty Cycle...139
PWM Output (Active-High)........................................133
PWM Output (Active-Low) ........................................134
Repeat Start Condition..............................................193
Reset, WDT, OST and Power-up Timer ...................252
Send Break Character Sequence.............................168
Slave Synchronization ..............................................182
SPI Mode Timing (Master Mode) SPI Mode
Master Mode Timing Diagram ..........................181
SPI Mode Timing (Slave Mode with CKE = 0)..........183
SPI Mode Timing (Slave Mode with CKE = 1)..........183
Stop Condition Receive or Transmit.........................198
Synchronous Reception (Master Mode, SREN) .......172
Synchronous Transmission.......................................170
Synchronous Transmission (Through TXEN) ...........170
Time-out Sequence
Case 1 ..............................................................212
Case 2 ..............................................................212
Case 3 ..............................................................212
Timer0 and Timer1 External Clock ...........................254
Timer1 Incrementing Edge..........................................78
Two Speed Start-up....................................................70
Wake-up from Interrupt.............................................223
Timing Parameter Symbology...........................................248
TRISA .................................................................................39
TRISA Register...................................................................39
TRISB .................................................................................47
TRISB Register...................................................................48
TRISC .................................................................................53
TRISC Register...................................................................53
TRISD .................................................................................57
TRISD Register...................................................................57
TRISE .................................................................................59
TRISE Register...................................................................59
Two-Speed Clock Start-up Mode........................................69
TXREG..............................................................................151
TXSTA Register................................................................158
BRGH Bit ..................................................................161
U
Ultra Low-Power Wake-up................................16, 18, 40, 41
V
Voltage Reference.
See
Comparator Voltage
Reference (CV
REF
)
Voltage References
Associated Registers.................................................. 97
VP6 Stabilization ........................................................ 94
V
REF
.
S
EE
ADC Reference Voltage
W
Wake-up on Break............................................................ 166
Wake-up Using Interrupts................................................. 222
Watchdog Timer (WDT).................................................... 220
Associated Registers................................................ 221
Clock Source ............................................................ 220
Modes....................................................................... 220
Period ....................................................................... 220
Specifications ........................................................... 253
Waveform for Slave Mode General Call Address
Sequence ................................................................. 188
WCOL............................................................... 192, 194, 197
WCOL Status Flag............................................ 192, 194, 197
WDTCON Register........................................................... 221
WPUB Register................................................................... 49
WWW Address ................................................................. 283
WWW, On-Line Support..................................................... 12