參數(shù)資料
型號(hào)： PIC16F883
廠商： Microchip Technology Inc.
英文描述： 28/40/44-Pin, Enhanced Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology
中文描述： 28/40/44-Pin，增強(qiáng)基于閃存的納瓦技術(shù)的8位CMOS微控制器
文件頁(yè)數(shù)： 188/288頁(yè)
文件大?。?/td> 2477K
代理商： PIC16F883
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PIC16F882/883/884/886/887
DS41291D-page 186
Preliminary
2007 Microchip Technology Inc.
13.4.1.1
Addressing
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the eight bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a)
The SSPSR register value is loaded into the
SSPBUF register.
b)
The buffer full bit BF is set.
c)
An ACK pulse is generated.
d)
MSSP interrupt flag bit, SSPIF of the PIR1
register, is set on the falling edge of the ninth
SCL pulse (interrupt is generated, if enabled).
In 10-bit address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSb) of the first address byte specify if this is a 10-bit
address. The R/W bit (SSPSTAT register) must specify
a write so the slave device will receive the second
address byte. For a 10-bit address, the first byte would
equal
‘1111 0 A9 A8 0’
, where
A9
and
A8
are the
two MSb’s of the address.
The sequence of events for 10-bit addressing is as
follows, with steps 7-9 for slave-transmitter:
1.
Receive first (high) byte of address (bit SSPIF of
the PIR1 register and bits BF and UA of the
SSPSTAT register are set).
2.
Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
3.
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4.
Receive second (low) byte of address (bits
SSPIF, BF, and UA are set).
5.
Update the SSPADD register with the first (high)
byte of address. If match releases SCL line, this
will clear bit UA.
6.
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7.
Receive Repeated Start condition.
8.
Receive first (high) byte of address (bits SSPIF
and BF are set).
9.
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
13.4.1.2
Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT register)
is set, or bit SSPOV (SSPCON register) is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit SSPIF of the PIR1 register must be
cleared in software. The SSPSTAT register is used to
determine the status of the byte.
13.4.1.3
Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR regis-
ter. Then pin RC3/SCK/SCL should be enabled by set-
ting bit CKP (SSPCON register). The master must
monitor the SCL pin prior to asserting another clock
pulse. The slave devices may be holding off the master
by stretching the clock. The eight data bits are shifted
out on the falling edge of the SCL input. This ensures
that the SDA signal is valid during the SCL high time
(Figure 13-8).
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the
master-receiver is latched on the rising edge of the
ninth SCL input pulse. If the SDA line is high (not ACK),
then the data transfer is complete. When the ACK is
latched by the slave, the slave logic is reset and the
slave monitors for another occurrence of the Start bit. If
the SDA line was low (ACK), the transmit data must be
loaded into the SSPBUF register, which also loads the
SSPSR register. Pin RC3/SCK/SCL should be enabled
by setting bit CKP.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PIC16F883-E/ML 功能描述:8位微控制器 -MCU 7KB Flash 256 RAM 25 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F883-E/SO 功能描述:8位微控制器 -MCU 7KB Flash 256 RAM 25 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F883-E/SP 功能描述:8位微控制器 -MCU 7KB Flash 256 RAM 25 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F883-E/SS 功能描述:8位微控制器 -MCU 7KB Flash 256 RAM 25 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F883-I/ML 功能描述:8位微控制器 -MCU 7KB Flash 256 RAM 25 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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