PIC16(L)F1512/3
DS41624B-page 106
Preliminary
2012 Microchip Technology Inc.
12.1
Alternate Pin Function
The Alternate Pin Function Control (APFCON) register
is used to steer specific peripheral input and output
functions between different pins. The APFCON register
is shown in Register 12-1. For this device family, the
following functions can be moved between different
pins.
SS (Slave Select)
CCP2
These bits have no effect on the values of any TRIS
register. PORT and TRIS overrides will be routed to the
correct pin. The unselected pin will be unaffected.
REGISTER 12-1:
APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER
U-0
R/W-0/0
—
SSSEL
CCP2SEL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Unimplemented:
Read as ‘0’
bit 1
SSSEL:
Pin Selection bit
0 =SS function is on RA5
1 =SS function is on RA0
bit 0
CCP2SEL:
Pin Selection bit
0 =
CCP2 function is on RC1
1 =
CCP2 function is on RB3
