
2002 Microchip Technology Inc.
DS41120B-page 57
PIC16C717/770/771
8.3.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
PWM duty cycle = (CCPR1L:CCP1CON<5:4>)
T
OSC
(TMR2 prescale value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2 con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
Maximum PWM resolution (bits) for a given PWM fre-
quency:
8.3.3
PWM OUTPUT CONFIGURATIONS
The PWM1M1 bits in the CCP1CON register allows
one of the following configurations:
Single output
Half-Bridge output
Full-Bridge output, Forward mode
Full-Bridge output, Reverse mode
In the Single Output mode, the RB3/CCP1/P1A pin is
used as the PWM output. Since the CCP1 output is
multiplexed with the PORTB<3> data latch, the
TRISB<3> bit must be cleared to make the CCP1 pin
an output.
FIGURE 8-4:
SINGLE PWM OUTPUT
FIGURE 8-5:
EXAMPLE OF SINGLE
OUTPUT APPLICATION
In the Half-Bridge Output mode, two pins are used as
outputs. The RB3/CCP1/P1A pin has the PWM output
signal, while the RB5/SDO/P1B pin has the comple-
mentary PWM output signal. This mode can be used
for half-bridge applications, as shown on Figure 8-7, or
for full-bridge applications, where four power switches
are being modulated with two PWM signal.
Since the P1A and P1B outputs are multiplexed with
the PORTB<3> and PORTB<5> data latches, the
TRISB<3> and TRISB<5> bits must be cleared to con-
figure P1A and P1B as outputs.
In Half-Bridge Output mode, the programmable dead-
band delay can be used to prevent shoot-through cur-
rent in bridge power devices. See Section 8.3.5 for
more details of the deadband delay operations.
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
OSC
F
2
log
-F
log
-----------------------------bits
=
Period
Duty Cycle
(1)
(1)
Note 1:
At this time, the TMR2 register is equal to the PR2 register.
2:
Output signal is shown as asserted high.
CCP1
(2)
C
PIC16C717/770/771
CCP1
R
Vout
Using PWM as
a D/A Converter
PIC16C717/770/771
CCP1
Using PWM to
Drive a Power
Load
V+
L
O
A
D