PIC16C717/770/771
DS41120B-page 54
2002 Microchip Technology Inc.
TABLE 8-1:
ECCP MODE - TIMER
RESOURCE
8.1
Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the 16-
bit value of the TMR1 register when an event occurs on
pin CCP1. An event is defined as:
every falling edge
every rising edge
every 4th rising edge
every 16th rising edge
An event is selected by control bits CCP1M<3:0>
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. It must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value will be lost.
8.1.1
CCP1 PIN CONFIGURATION
In Capture mode, the CCP1 pin should be configured
as an input by setting the TRISB<3> bit.
8.1.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode. In Asynchronous Counter mode,
the capture operation may not work.
8.1.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in Operating mode.
8.1.4
ECCP PRESCALER
There are three prescaler settings, specified by bits
CCP1M<3:0>. Whenever the ECCP module is turned
off or the ECCP module is not in Capture mode, the
prescaler counter is cleared. This means that any
RESET will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore the first capture may be from
a non-zero prescaler. Example 8-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 8-1:
Changing Between
Capture Prescalers
FIGURE 8-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
8.2
Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the CCP1 pin is:
driven High
driven Low
toggle output (High to Low or Low to High)
remains Unchanged
The action on the pin is based on the value of control
bits CCP1M<3:0>. At the same time, interrupt flag bit
CCP1IF is set.
Changing the ECCP mode select bits to the clear out-
put on Match mode (CCP1M<3.0> = “1000”) presets
the CCP1 output latch to the logic 1 level. Changing the
ECCP mode select bits to the clear output on Match
mode (CCP1M<3:0> = “1001”) presets the CCP1 out-
put latch to the logic 0 level.
8.2.1
CCP1 PIN CONFIGURATION
The user must configure the CCP1 pin as an output by
clearing the appropriate TRISB bit.
8.2.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the ECCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
ECCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
Note:
If the RB3/CCP1/P1A pin is configured as
an output, a write to the port can cause a
capture condition.
Note:
Clearing the CCP1CON register will force
the CCP1 compare output latch to the
default low level. This is not the port data
latch.
CLRF
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; value and ECCP ON
MOVWF CCP1CON
; Load CCP1CON with
; this value
CCP1CON
; Turn ECCP module off
CCPR1H
CCPR1L
TMR1H
TMR1L
Set flag bit CCP1IF
(PIR1<2>)
Capture
Enable
Q’s
CCP1CON<3:0>
RB3/CCP1/
P1A Pin
Prescaler
3 1, 4, 16
and
edge detect