PIC16C62B/72A
DS35008B-page 102
Preliminary
1998 Microchip Technology Inc.
FIGURE 13-17: A/D CONVERSION TIMING
TABLE 13-14: A/D CONVERSION REQUIREMENTS
Param
No.
130
T
AD
A/D clock period
Sym
Characteristic
Min
Typ
Max
Unit
s
μ
s
μ
s
μ
s
μ
s
T
AD
Conditions
PIC16CXX
1.6
2.0
2.0
3.0
11
—
—
4.0
6.0
—
—
—
6.0
9.0
11
T
OSC
based, V
REF
≥
3.0V
T
OSC
based, V
REF
full range
A/D RC Mode
A/D RC Mode
PIC16LCXX
PIC16CXX
PIC16LCXX
131
T
CNV
Conversion time (not including S/H
time) (Note 1)
T
ACQ
Acquisition time
132
Note 2
5*
20
—
—
—
μ
s
μ
s
The minimum time is the
amplifier settling time. This
may be used if the "new" input
voltage has not changed by
more than 1 LSb (i.e., 20.0 mV
@ 5.12V) from the last sam-
pled voltage (as stated on
C
HOLD
).
If the A/D clock source is
selected as RC, a time of T
CY
is added before the A/D clock
starts. This allows the
SLEEP
instruction to be executed.
134
T
GO
Q4 to A/D clock start
—
T
OSC
/2
—
—
135
Tswc Switching from convert
→
sample
time
* These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25
°
C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1:
ADRES register may be read on the following T
CY
cycle.
2:
See Section 9.1 for min conditions.
1.5
—
—
T
AD
131
130
132
BSF ADCON0, GO
134
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(Tosc/2)
(1)
7
6
5
4
3
2
1
0
Note 1:
If the A/D clock source is selected as RC, a time of T
CY
is added before the A/D clock starts. This
allows the
SLEEP
instruction to be executed.
1 T
CY
