參數(shù)資料
型號(hào): PIC16C433T-I/SO
廠商: Microchip Technology
文件頁數(shù): 119/126頁
文件大?。?/td> 0K
描述: IC MCU CMOS 8BIT 10MHZ 2K 18SOIC
標(biāo)準(zhǔn)包裝: 1,100
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 10MHz
連通性: LIN(本地互連網(wǎng)絡(luò))
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 5
程序存儲(chǔ)器容量: 3.5KB(2K x 14)
程序存儲(chǔ)器類型: OTP
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 18-SOIC(0.295",7.50mm 寬)
包裝: 帶卷 (TR)
92
4378C–AVR–09/08
AT90PWM1
Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see Table 26. Modes of operation supported by the Timer/Counter
unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of
Pulse Width Modulation (PWM) modes (see “Modes of Operation” on page 84).
Notes:
1. MAX
= 0xFF
2. BOTTOM = 0x00
14.8.2
Timer/Counter Control Register B – TCCR0B
Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit,
an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is
changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a
strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the
forced compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0A as TOP.
The FOC0A bit is always read as zero.
Bit 6 – FOC0B: Force Output Compare B
The FOC0B bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit,
an immediate Compare Match is forced on the Waveform Generation unit. The OC0B output is
changed according to its COM0B1:0 bits setting. Note that the FOC0B bit is implemented as a
Table 26. Waveform Generation Mode Bit Description
Mode
WGM02
WGM01
WGM00
Timer/Count
er Mode of
Operation
TOP
Update of
OCRx at
TOV Flag
Set on
0
Normal
0xFF
Immediate
MAX
1
001
PWM, Phase
Correct
0xFF
TOP
BOTTOM
2
0
1
0
CTC
OCRA
Immediate
MAX
3
011
Fast PWM
0xFF
TOP
MAX
4
100
Reserved
5
101
PWM, Phase
Correct
OCRA
TOP
BOTTOM
6
110
Reserved
7
111
Fast PWM
OCRA
TOP
Bit
7
6
5
4
3
2
1
0
FOC0A
FOC0B
WGM02
CS02
CS01
CS00
TCCR0B
Read/Write
W
R
R/W
Initial Value
0
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