參數(shù)資料
型號(hào): PIC12F675
廠商: Microchip Technology Inc.
英文描述: 8-Pin, 8-Bit CMOS Enhanced FLASH Microcontroller with A/D Converter and EEPROM Data Memory(-2.5~5.5V,具ADC,閃速微控制器)
中文描述: 8引腳,8位閃存微控制器的CMOS增強(qiáng)與A / D轉(zhuǎn)換器和EEPROM數(shù)據(jù)存儲(chǔ)器(-2.5?5.5V的,具藝術(shù)發(fā)展局,閃速微控制器)
文件頁數(shù): 138/170頁
文件大?。?/td> 4191K
代理商: PIC12F675
PIC16F62X
DS40300C-page 136
Preliminary
2003 Microchip Technology Inc.
TABLE 17-4:
EXTERNAL CLOCK TIMING REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ
Max
Units
Conditions
Fosc
External CLKIN Frequency
(1)
DC
4
MHz XT and ER Osc mode,
V
DD
= 5.0V
DC
20
MHz HS Osc mode
DC
200
kHz
LP Osc mode
Oscillator Frequency
(1)
4
MHz ER Osc mode, V
DD
= 5.0V
0.1
4
MHz XT Osc mode
1
20
200
MHz
kHz
HS Osc mode
LP Osc mode
3.65
4
4.28
MHz INTRC mode (fast), V
DD
= 5.0V
37
kHz
INTRC mode (slow)
4
INTRC Internal Calibrated RC
3.65
4.00
4.28
MHz V
DD
= 5.0V
5
ER
External Biased ER Frequency
External CLKIN Period
(1)
10 kHz
8 MHz
V
DD
= 5.0V
1
Tosc
250
ns
XT and ER Osc mode
50
ns
μ
s
HS Osc mode
5
LP Osc mode
Oscillator Period
(1)
250
ns
ER Osc mode
250
10,000
ns
XT Osc mode
50
1,000
ns
μ
s
HS Osc mode
5
LP Osc mode
250
ns
μ
s
INTRC mode (fast)
27
INTRC mode (slow)
2
Tcy
Instruction Cycle Time
1.0
T
CY
DC
ns
T
CY
= 4/F
OSC
3
TosL,
TosH
External CLKIN (OSC1) High
External CLKIN Low
100 *
ns
XT oscillator, T
OSC
L/H duty
cycle*
*
These parameters are characterized but not tested.
Data in “Typ” column is at 5.0V, 25
°
C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1:
Instruction cycle period (Tcy) equals four times the input oscillator time-based period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “Min.”
values with an external clock applied to the OSC1 pin. When an external clock input is used, the “Max”
cycle time limit is “DC” (no clock) for all devices.
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