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參數(shù)資料
| 型號： | PIC12F1840T-I/SN |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 75/122頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU 7KB FLASH 256B RAM XLP 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 3,300 |
| 系列： | PIC® XLP™ 12F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 32MHz |
| 連通性： | I²C，LIN，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 5 |
| 程序存儲器容量： | 7KB（4K x 14） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 256 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.3 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 4x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 包裝： | 帶卷 (TR) |
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PIC12(L)F1840
DS41441B-page 56
Preliminary
2011 Microchip Technology Inc.
5.3
Clock Switching
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS) bits of the OSCCON
register. The following clock sources can be selected
using the SCS bits:
Default system oscillator determined by FOSC
bits in Configuration Word 1
Timer1 32 kHz crystal oscillator
Internal Oscillator Block (INTOSC)
5.3.1
SYSTEM CLOCK SELECT (SCS)
BITS
The System Clock Select (SCS) bits of the OSCCON
register selects the system clock source that is used for
the CPU and peripherals.
When the SCS bits of the OSCCON register = 00,
the system clock source is determined by value of
the FOSC<2:0> bits in the Configuration Word 1.
When the SCS bits of the OSCCON register = 01,
the system clock source is the Timer1 oscillator.
When the SCS bits of the OSCCON register = 1x,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<3:0>
bits of the OSCCON register. After a Reset, the
SCS bits of the OSCCON register are always
cleared.
When switching between clock sources, a delay is
required to allow the new clock to stabilize. These oscil-
lator delays are shown in Table 5-1.
5.3.2
OSCILLATOR START-UP TIME-OUT
STATUS (OSTS) BIT
The Oscillator Start-up Time-out Status (OSTS) bit of
the OSCSTAT register indicates whether the system
clock is running from the external clock source, as
defined by the FOSC<2:0> bits in the Configuration
Word 1, or from the internal clock source. In particular,
OSTS indicates that the Oscillator Start-up Timer
(OST) has timed out for LP, XT or HS modes. The OST
does not reflect the status of the Timer1 Oscillator.
5.3.3
TIMER1 OSCILLATOR
The Timer1 Oscillator is a separate crystal oscillator
associated with the Timer1 peripheral. It is optimized
for timekeeping operations with a 32.768 kHz crystal
connected between the T1OSO and T1OSI device
pins.
The Timer1 oscillator is enabled using the T1OSCEN
control bit in the T1CON register. See Section 21.0
for more
information about the Timer1 peripheral.
5.3.4
TIMER1 OSCILLATOR READY
(T1OSCR) BIT
The user must ensure that the Timer1 Oscillator is
ready to be used before it is selected as a system clock
source. The Timer1 Oscillator Ready (T1OSCR) bit of
the OSCSTAT register indicates whether the Timer1
oscillator is ready to be used. After the T1OSCR bit is
set, the SCS bits can be configured to select the Timer1
oscillator.
Note:
Any automatic clock switch, which may
occur
from
Two-Speed
Start-up
or
Fail-Safe Clock Monitor, does not update
the SCS bits of the OSCCON register. The
user can monitor the OSTS bit of the
OSCSTAT register to determine the current
system clock source.
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