參數(shù)資料
型號： PI7C8154-33
英文描述： PCI Bridge | 2-Port PCI-to-PCI Bridge
中文描述： PCI橋| 2端口PCI至PCI橋
文件頁數(shù)： 65/115頁
文件大?。?/td> 879K
代理商： PI7C8154-33
PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 65 of 115
July 31, 2003 – Revision 1.031
!
PI7C8150B has detected P_PERR_L asserted on an upstream posted write transaction
or S_PERR_L asserted on a downstream posted write transaction.
!
!
PI7C8150B did not detect the parity error as a target of the posted write transaction.
The parity error response bit on the command register and the parity error response bit
on the bridge control register must both be set.
!
The SERR_L enable bit must be set in the command register.
Table 6-7. Assertion of P_SERR_L for Data Parity Errors
P_SERR_L
Transaction Type
Direction
Bus Where Error
Was Detected
Primary /
Secondary Parity
Error Response
Bits
x / x
x / x
x / x
x / x
x / x
1 / 1
1 / 1
x / x
x / x
x / x
x / x
x / x
1 (de-asserted)
1
1
1
1
0
2
(asserted)
0
3
1
1
1
1
1
X
= don’t care
2
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
3
The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
6.4
SYSTEM ERROR (SERR_L) REPORTING
PI7C8150B uses the P_SERR_L signal to report conditionally a number of system error
conditions in addition to the special case parity error conditions described in Section 6.2.3.
Whenever assertion of P_SERR_L is discussed in this document, it is assumed that the
following conditions apply:
!
For PI7C8150B to assert P_SERR_L for any reason, the SERR_L enable bit must be
set in the command register.
!
Whenever PI7C8150B asserts P_SERR_L, PI7C8150B must also set the signaled
system error bit in the status register.
In compliance with the PCI-to-PCI Bridge Architecture Specification, PI7C8150B asserts
P_SERR_L when it detects the secondary SERR_L input, S_SERR_L, asserted and the
SERR_L forward enable bit is set in the bridge control register. In addition, PI7C8150B
also sets the received system error bit in the secondary status register.
PI7C8150B also conditionally asserts P_SERR_L for any of the following reasons:
!
Target abort detected during posted write transaction
相關(guān)PDF資料
PDF描述
PI7C8150 PCI Bridge | 2-Port PCI-to-PCI Bridge
PI7C8150-33 PCI Bridge | 2-Port PCI-to-PCI Bridge
PI7C8150A PCI Bridge | 2-Port PCI-to-PCI Bridge
PI7C8150A-33 PCI Bridge | 2-Port PCI-to-PCI Bridge
PI7C8150B PCI Bridge | Asynchronous 2-Port PCI Bridge
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C8154ANA 功能描述:外圍驅(qū)動器與原件 - PCI 64-Bit/66MHz 2-Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8154ANAE 功能描述:外圍驅(qū)動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8154ANAE-33 功能描述:外圍驅(qū)動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8154B 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT 64 BIT 66MHZ PCI TO PCI BRIDGE
PI7C8154BNA 制造商:Pericom Semiconductor Corporation 功能描述:
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