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參數(shù)資料
| 型號(hào)： | PI7C8154-33 |
| 英文描述： | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| 中文描述： | PCI橋| 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 59/115頁 |
| 文件大?。?/td> | 879K |
| 代理商： | PI7C8154-33 |
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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 59 of 115
July 31, 2003 – Revision 1.031
6.2.4
POSTED WRITE TRANSACTIONS
During downstream posted write transactions, when PI7C8150B responds as a target, it
detects a data parity error on the initiator (primary) bus and the following events occur:
!
PI7C8150B asserts P_PERR_L two cycles after the data transfer, if the parity error
response bit is set in the command register of primary interface.
!
PI7C8150B sets the parity error detected bit in the status register of the primary
interface.
!
PI7C8150B captures and forwards the bad parity condition to the secondary bus.
!
PI7C8150B completes the transaction normally.
Similarly, during upstream posted write transactions, when PI7C8150B responds as a
target, it detects a data parity error on the initiator (secondary) bus, the following events
occur:
!
PI7C8150B asserts S_PERR_L two cycles after the data transfer, if the parity error
response bit is set in the bridge control register of the secondary interface.
!
PI7C8150B sets the parity error detected bit in the status register of the secondary
interface.
!
PI7C8150B captures and forwards the bad parity condition to the primary bus.
!
PI7C8150B completes the transaction normally.
During downstream write transactions, when a data parity error is reported on the target
(secondary) bus by the target’s assertion of S_PERR_L, the following events occur:
!
PI7C8150B sets the data parity detected bit in the status register of secondary
interface, if the parity error response bit is set in the bridge control register of the
secondary interface.
!
PI7C8150B asserts P_SERR_L and sets the signaled system error bit in the status
register, if all the following conditions are met:
!
The SERR_L enable bit is set in the command register.
!
The posted write parity error bit of P_SERR_L event disable register is not
set.
!
The parity error response bit is set in the bridge control register of the
secondary interface.
!
The parity error response bit is set in the command register of the primary
interface.
!
PI7C8150B has not detected the parity error on the primary (initiator) bus
which the parity error is not forwarded from the primary bus to the
secondary bus.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C8150 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150B | PCI Bridge | Asynchronous 2-Port PCI Bridge |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8154ANA | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64-Bit/66MHz 2-Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154ANAE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154ANAE-33 | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154B | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT 64 BIT 66MHZ PCI TO PCI BRIDGE |
| PI7C8154BNA | 制造商:Pericom Semiconductor Corporation 功能描述: |
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