參數(shù)資料
型號(hào)： PI7C8150MA-33
廠商： Pericom Semiconductor Corp.
英文描述： 2-Port PCI-to-PCI Bridge
中文描述： 2端口PCI至PCI橋
文件頁數(shù)： 30/106頁
文件大小： 904K
代理商： PI7C8150MA-33
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
20
August 22, 2002 – Revision 1.02
The bus command is a configuration read or configuration write transaction.
Lowest two address bits P_AD[1:0] must be 00b.
Signal P_IDSEL must be asserted.
PI7C8150 limits all configuration access to a single DWORD data transfer and returns
target-disconnect with the first data transfer if additional data phases are requested.
Because read transactions to configuration space do not have side effects, all bytes in the
requested DWORD are returned, regardless of the value of the byte enable bits.
Type 0 configuration write and read transactions do not use data buffers; that is, these
transactions are completed immediately, regardless of the state of the data buffers. The
PI7C8150 ignores all Type 0 transactions initiated on the secondary interface.
3.7.2
TYPE 1 TO TYPE 0 CONVERSION
Type 1 configuration transactions are used specifically for device configuration in a
hierarchical PCI bus system. A PCI-to-PCI bridge is the only type of device that should
respond to a Type 1 configuration command. Type 1 configuration commands are used
when the configuration access is intended for a PCI device that resides on a PCI bus other
than the one where the Type 1 transaction is generated.
PI7C8150 performs a Type 1 to Type 0 translation when the Type 1 transaction
is generated on the primary bus and is intended for a device attached directly to the
secondary bus. PI7C8150 must convert the configuration command to a Type 0 format so
that the secondary bus device can respond to it. Type 1 to Type 0 translations are
performed only in the downstream direction; that is, PI7C8150 generates a Type 0
transaction only on the secondary bus, and never on the primary bus.
PI7C8150 responds to a Type 1 configuration transaction and translates it into a Type 0
transaction on the secondary bus when the following conditions are met during the address
phase:
The lowest two address bits on P_AD[1:0] are 01b.
The bus number in address field P_AD[23:16] is equal to the value in the secondary
bus number register in configuration space.
The bus command on P_CBE[3:0] is a configuration read or configuration write
transaction.
When PI7C8150 translates the Type 1 transaction to a Type 0 transaction on
the secondary interface, it performs the following translations to the address:
Sets the lowest two address bits on S_AD[1:0].
Decodes the device number and drives the bit pattern specified in Table 4–6 on
S_AD[31:16] for the purpose of asserting the device’s IDSEL signal.
Sets S_AD[15:11] to 0.
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