參數(shù)資料
型號(hào)： PI7C8150MA-33
廠商： Pericom Semiconductor Corp.
英文描述： 2-Port PCI-to-PCI Bridge
中文描述： 2端口PCI至PCI橋
文件頁(yè)數(shù)： 25/106頁(yè)
文件大?。?/td> 904K
代理商： PI7C8150MA-33
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
15
August 22, 2002 – Revision 1.02
latency. PI7C78150 returns a target disconnect to the initiator when it reaches the aligned
address boundaries under conditions shown in Table 4–3.
Table 4-3. Write Transaction Disconnect Address Boundaries
Type of Transaction
Delayed Write
Posted Memory Write
bit = 0
Posted Memory Write
Condition
All
Memory write disconnect control
Aligned Address Boundary
Disconnects after one data transfer
4KB aligned address boundary
Memory write disconnect control
bit = 1
Cache line size 1, 2, 4, 8, 16
Disconnects at cache line boundary
Posted Memory Write and
Invalidate
Posted Memory Write and
Invalidate
4KB aligned address boundary
Cache line size = 1, 2, 4, 8, 16
Cache line boundary if posted memory
write data FIFO does not have enough
space for the cache line
Note 1.
Memory write disconnect control bit is bit 1 of the chip control register at offset 40h in the
configuration space.
3.5.5
BUFFERING MULTIPLE WRITE TRANSACTIONS
PI7C8150 continues to accept posted memory write transactions as long as space for at
least one DWORD of data in the posted write data buffer remains. If the posted write data
buffer fills before the initiator terminates the write transaction, PI7C8150 returns a target
disconnect to the initiator.
Delayed write transactions are posted as long as at least one open entry in
the delayed transaction queue exists. Therefore, several posted and delayed write
transactions can exist in data buffers at the same time. See Chapter 6 for information about
how multiple posted and delayed write transactions are ordered.
3.5.6
FAST BACK-TO-BACK TRANSACTIONS
PI7C8150 can recognize and post fast back-to-back write transactions.
When PI7C8150 cannot accept the second transaction because of buffer
space limitations, it returns a target retry to the initiator. The fast back-to-back enable bit
must be set in the command register for upstream write transactions, and in the bridge
control register for downstream write transactions.
3.6
READ TRANSACTIONS
Delayed read forwarding is used for all read transactions crossing PI7C8150.
Delayed read transactions are treated as either prefetchable or non-prefetchable. Table 4-5
shows the read behavior, prefetchable or non-prefetchable, for each
type of read operation.
3.6.1
PREFETCHABLE READ TRANSACTIONS
A prefetchable read transaction is a read transaction where PI7C8150 performs speculative
DWORD reads, transferring data from the target before it is requested from the initiator.
This behavior allows a prefetchable read transaction to consist of multiple data transfers.
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