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參數(shù)資料
| 型號： | PI6CU877NF |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | PLL Clock Driver for 1.8V DDR2 Memory |
| 中文描述： | PLL時鐘驅(qū)動器1.8V的DDR2內(nèi)存 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 543K |
| 代理商： | PI6CU877NF |
5
PS8689B 08/05/04
PI6CU877
PLL Clock Driver for
1.8V DDR2 Memory
Timing Requirements
(Over recommended operating free-air temperature)
Symbol
Decription
AV
DD
, V
DDQ
= 1.8V ±0.1V
Min.
25
160
40
Units
Max.
300
270
60
15
8
FCK
Operation clock frequency
(7, 8)
Application clock frequency
(7, 9)
Input clock duty cycle
Stabalization time
(10)
Device power down
(10)
MHz
t
DC
t
L
t
OFF
%
μs
ns
Notes:
7. The PLL is able to handle spread spectrum induced skew.
8. Operating clock frequency indicates a range over which the PLL is able to lock, but in which it is not required to meet the other
timing parameters. (Used for low-speed debug).
9. Application clock frequency indicates a range over which the PLL must meet all timing parameters.
10. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference
signal after power up . During normal operation, the stabilization time is also the time required for the integrated PLL circuit to
obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down
mode and later return to active operation. CK and CK maybe left floating after they have been driven low for one complete clock cycle.
DC Specifications
Param-
eter
V
IK
Description
Test Condition
AV
DD
,
V
DDQ
1.7V
1.7 to
1.9V
1.7
Min.
Typ.
Max.
Units
All Inputs
I
I
= -18mA
1.2
V
V
OH
HIGH output voltage
I
OH
= -100μA
V
DDQ
-0.2
1.1
100
I
OH
= -9mA
OE = L, V
ODL
= 100mV
I
ODL
Output disabled low current
Output differenital voltage, the magniture of the difference
between the true and complimentary outputs, see fig. 9 for
dimentions
CK, CK
OE, OS, FB
IN
, FB
IN
Static Supple current, I
DDQ
+ I
ADD
Dynamic supply current, I
DDQ
+
I
ADD
, see note 6 for CPD calcula-
tion
CK, CK
FB
IN
, FB
IN
CK, CK
FB
IN
, FB
IN
1.7V
μA
V
OD
0.6
V
I
I
V
I
= V
DDQ
or GND
V
I
= V
DDQ
or GND
CK and CK = L
CK and CK = 270MHz,
all outputs are open (not
connected to a PCB)
V
I
= V
DDQ
or GND
V
I
= V
DDQ
or GND
V
I
= V
DDQ
or GND
V
I
= V
DDQ
or GND
1.9V
±250
±10
500
μA
I
DDLD
I
DD
300
mA
CI
1.8V
2
2
3
3
pF
CI()
0.25
0.25
Notes
:
6. Total I
DD
= I
DDQ +
I
ADD
= F
CK
*C
PD
*V
DDQ
, solving for C
PD
= (I
DDQ
+ I
ADD
)/(F
CK
*V
DDQ
) where F
CK
is the input frequency, V
DDQ
is the
power supply and C
PD
is the Power Dissipation Capacitance.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI6CU877NFE | 功能描述:鎖相環(huán) - PLL PLL Clock Driver for 1.8V DDR2 RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6CU877NFEX | 功能描述:鎖相環(huán) - PLL PLL Clock Driver for 1.8V DDR2 RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6CU877NFX | 制造商:Pericom Semiconductor Corporation 功能描述:Zero Delay PLL Clock Driver Single 125MHz to 300MHz 52-Pin VFBGA T/R |
| PI6CUA877NFE | 功能描述:鎖相環(huán) - PLL PLL Clock Driver for 1.8V DDR2 RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6CUA877NFEX | 功能描述:鎖相環(huán) - PLL PLL Clock Driver for 1.8V DDR2 RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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