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參數(shù)資料
| 型號： | PHP69NLT |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | TrenchMOS transistor Logic level FET |
| 中文描述： | TrenchMOS晶體管邏輯電平場效應管 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 78K |
| 代理商： | PHP69NLT |
Philips Semiconductors
Product specification
TrenchMOS
transistor
Logic level FET
PHP69N03LT, PHB69N03LT, PHD69N03LT
FEATURES
SYMBOL
QUICK REFERENCE DATA
V
DSS
= 25 V
’Trench’
technology
Very low on-state resistance
Fast switching
Stable off-state characteristics
High thermal cycling performance
Low thermal resistance
I
D
= 69 A
R
DS(ON)
≤
14 m
(V
GS
= 5 V)
R
DS(ON)
≤
12 m
(V
GS
= 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’
trench
’ technology.
The combination of very low on-state resistance and low switching losses make this device the optimum choice in high
speed computer motherboard d.c. to d.c. converters.
The PHP69N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB69N03LT is supplied in the SOT404 surface mounting package.
The PHD69N03LT is supplied in the SOT428 surface mounting package.
PINNING
SOT78 (TO220AB)
SOT404
SOT428
PIN
DESCRIPTION
1
gate
2
drain
1
3
source
tab
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
Drain-source voltage
V
DGR
Drain-gate voltage
V
GS
Gate-source voltage
V
GSM
Pulsed gate-source voltage
I
D
Continuous drain current
CONDITIONS
T
j
= 25 C to 175C
T
j
= 25 C to 175C; R
GS
= 20 k
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
25
25
±
15
±
20
69
48
240
125
175
UNIT
V
V
V
V
A
A
A
W
C
T
j
≤
150C
T
mb
= 25 C; V
GS
= 5 V
T
mb
= 100 C; V
GS
= 5 V
T
mb
= 25 C
T
mb
= 25 C
I
DM
P
D
T
j
, T
stg
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
d
g
s
1
2
3
tab
1
3
tab
2
1 2 3
tab
1
It is not possible to make connection to pin 2 of the SOT428 or SOT404 packages.
June 1998
1
Rev 1.400
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