參數(shù)資料
型號： PHB95NQ04LT
廠商： NXP SEMICONDUCTORS
元件分類： JFETs
英文描述： N-channel TrenchMOS logic level FET
中文描述： 75 A, 40 V, 0.01 ohm, N-CHANNEL, Si, POWER, MOSFET
封裝： PLASTIC, D2PAK-3
文件頁數(shù)： 5/12頁
文件大小： 90K
代理商： PHB95NQ04LT
Philips Semiconductors
PHB95NQ04LT
N-channel TrenchMOS logic level FET
Product data
Rev. 01 — 11 May 2004
5 of 12
9397 750 13166
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
6.
Characteristics
Table 5:
T
j
= 25
°
C unless otherwise specified.
Symbol Parameter
Static characteristics
V
(BR)DSS
drain-source breakdown voltage
Characteristics
Conditions
Min
Typ
Max
Unit
I
D
= 250
μ
A; V
GS
= 0 V
T
j
= 25
°
C
T
j
=
55
°
C
I
D
= 1 mA; V
DS
= V
GS
;
Figure 9
and
10
T
j
= 25
°
C
T
j
= 175
°
C
T
j
=
55
°
C
V
DS
= 40 V; V
GS
= 0 V
T
j
= 25
°
C
T
j
= 175
°
C
V
GS
=
±
15 V; V
DS
= 0 V
V
GS
= 10 V; I
D
= 25 A;
Figure 7
and
8
T
j
= 25
°
C
T
j
= 175
°
C
V
GS
= 5 V; I
D
= 25 A;
Figure 7
and
8
V
GS
= 4.5 V; I
D
= 25 A
40
36
-
-
-
-
V
V
V
GS(th)
gate-source threshold voltage
1
0.5
-
1.5
-
-
2
-
2.2
V
V
V
I
DSS
drain-source leakage current
-
-
-
-
-
2
1
500
100
μ
A
μ
A
nA
I
GSS
R
DSon
gate-source leakage current
drain-source on-state resistance
-
-
-
-
6.2
11.8
7.6
-
7
13.3
9
10
m
m
m
m
Dynamic characteristics
Q
g(tot)
total gate charge
Q
gs
gate-source charge
Q
gd
gate-drain (Miller) charge
C
iss
input capacitance
C
oss
output capacitance
C
rss
reverse transfer capacitance
t
d(on)
turn-on delay time
t
r
rise time
t
d(off)
turn-off delay time
t
f
fall time
Source-drain diode
V
SD
source-drain (diode forward) voltage I
S
= 25 A; V
GS
= 0 V;
Figure 12
t
rr
reverse recovery time
Q
r
recovered charge
I
D
= 25 A; V
DD
= 32 V; V
GS
= 5 V;
Figure 13
-
-
-
-
-
-
-
-
-
-
32.7
7.2
12.4
2700
450
210
29
106
108
89
-
-
-
-
-
-
-
-
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz;
Figure 11
V
DD
= 30 V; R
G
= 1.2
;
V
GS
= 5 V; R
G
= 10
-
-
-
0.85
57
47
1.2
-
-
V
ns
nC
I
S
= 20 A; dI
S
/dt =
100 A/
μ
s;
V
GS
= 0 V; V
R
= 30 V
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