參數(shù)資料
型號(hào)： PH28F640L18T85
廠商： INTEL CORP
元件分類： PROM
英文描述： StrataFlash Wireless Memory
中文描述： 4M X 16 FLASH 1.8V PROM, 85 ns, PBGA56
封裝： 0.75 MM PITCH, LEAD FREE, VFBGA-56
文件頁(yè)數(shù)： 51/106頁(yè)
文件大小： 1272K
代理商： PH28F640L18T85
Intel StrataFlash Wireless Memory (L18)
Datasheet
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
April 2005
51
During synchronous array and non-array read modes, the first word is output from the data buffer
on the next valid CLK edge after the initial access latency delay (see
Section 10.3.2, “Latency
Count” on page 52
). Subsequent data is output on valid CLK edges following a minimum delay.
However, for a synchronous non-array read, the same word of data will be output on successive
clock edges until the burst length requirements are satisfied.
Figure 14Figure 16
10.2.1
Burst Suspend
The Burst Suspend feature of the device can reduce or eliminate the initial access latency incurred
when system software needs to suspend a burst sequence that is in progress in order to retrieve data
from another device on the same system bus. The system processor can resume the burst sequence
later. Burst suspend provides maximum benefit in non-cache systems.
Burst accesses can be suspended during the initial access latency (before data is received) or after
the device has output data. When a burst access is suspended, internal array sensing continues and
any previously latched internal data is retained. A burst sequence can be suspended and resumed
without limit as long as device operation conditions are met.
Burst Suspend occurs when CE# is asserted, the current address has been latched (either ADV#
rising edge or valid CLK edge), CLK is halted, and OE# is deasserted. CLK can be halted when it
is at V
IH
or V
IL
. WAIT is in High-Z during OE# deassertion.
To resume the burst access, OE# is reasserted, and CLK is restarted. Subsequent CLK edges
resume the burst sequence.
Within the device, CE# and OE# gate WAIT. Therefore, during Burst Suspend WAIT is placed in
high-impedance state when OE# is deasserted and resumed active when OE# is re-asserted. See
Figure 17, “Burst Suspend Timing” on page 36
.
10.3
Read Configuration Register (RCR)
The RCR is used to select the read mode (synchronous or asynchronous), and it defines the
synchronous burst characteristics of the device. To modify RCR settings, use the Configure Read
Configuration Register command (see
Section 9.2, “Device Commands” on page 47
).
RCR contents can be examined using the Read Device Identifier command, and then reading from
<partition base address> + 0x05 (see
Section 15.2, “Read Device Identifier” on page 76
).
The RCR is shown in
Table 10
. The following sections describe each RCR bit.
Table 10.
Read Configuration Register Description (Sheet 1 of 2)
Read Configuration Register (RCR)
Read
Mode
RES
Latency Count
WAIT
Polarity
Data
Hold
WAIT
Delay
Burst
Seq
CLK
Edge
RES
RES
Burst
Wrap
Burst Length
RM
R
LC[2:0]
WP
DH
WD
BS
CE
R
R
BW
BL[2:0]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit
Name
Description
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