參數(shù)資料
型號： PH28F256L18T85
廠商： INTEL CORP
元件分類： PROM
英文描述： StrataFlash Wireless Memory
中文描述： 16M X 16 FLASH 1.8V PROM, 85 ns, PBGA79
封裝： 0.75 MM PITCH, LEAD FREE, VFBGA-79
文件頁數(shù)： 47/106頁
文件大?。?/td> 1272K
代理商： PH28F256L18T85
Intel StrataFlash Wireless Memory (L18)
Datasheet
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
April 2005
47
After initial power-up or reset, the device defaults to asynchronous Read Array, and the Status
Register is set to 0x80. Asserting RST# de-energizes all internal circuits, and places the output
drivers in High-Z. When RST# is asserted, the device shuts down the operation in progress, a
process which takes a minimum amount of time to complete. When RST# has been deasserted, the
device is reset to asynchronous Read Array state.
Note:
If RST# is asserted during a program or erase operation, the operation is terminated and the
memory contents at the aborted location (for a program) or block (for an erase) are no longer valid,
because the data may have been only partially written or erased.
When returning from a reset (RST# deasserted), a minimum wait is required before the initial read
access outputs valid data. Also, a minimum delay is required after a reset before a write cycle can
be initiated. After this wake
-
up interval passes, normal operation is restored. See
Section 7.0, “AC
Characteristics” on page 28
for details about signal-timing.
9.2
Device Commands
Device operations are initiated by writing specific device commands to the Command User
Interface (CUI). See
Table 8, “Command Bus Cycles” on page 47
.
Several commands are used to modify array data including Word Program and Block Erase
commands. Writing either command to the CUI initiates a sequence of internally
-
timed functions
that culminate in the completion of the requested task. However, the operation can be aborted by
either asserting RST# or by issuing an appropriate suspend command.
Table 8.
Command Bus Cycles (Sheet 1 of 2)
Mode
Command
Bus
Cycles
First Bus Cycle
Second Bus Cycle
Oper
Addr
1
Data
2
Oper
Addr
1
Data
2
Read
Read Array
1
Write
PnA
0xFF
Read Device Identifier
≥
2
Write
PnA
0x90
Read
PBA+IA
ID
CFI Query
≥
2
Write
PnA
0x98
Read
PnA+QA QD
Read Status Register
2
Write
PnA
0x70
Read
PnA
SRD
Clear Status Register
1
Write
X
0x50
Program
Word Program
2
Write
WA
0x40/
0x10
Write
WA
WD
Buffered Program
3
>
2
Write
WA
0xE8
Write
WA
N - 1
Buffered Enhanced Factory Program
(Buffered EFP)
4
>
2
Write
WA
0x80
Write
WA
0xD0
Erase
Block Erase
2
Write
BA
0x20
Write
BA
0xD0
Suspend
Program/Erase Suspend
1
Write
X
0xB0
Program/Erase Resume
1
Write
X
0xD0
Block
Locking/
Unlocking
Lock Block
2
Write
BA
0x60
Write
BA
0x01
Unlock Block
2
Write
BA
0x60
Write
BA
0xD0
Lock-down Block
2
Write
BA
0x60
Write
BA
0x2F
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