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參數(shù)資料
| 型號： | PH28F256L18T85 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | StrataFlash Wireless Memory |
| 中文描述： | 16M X 16 FLASH 1.8V PROM, 85 ns, PBGA79 |
| 封裝： | 0.75 MM PITCH, LEAD FREE, VFBGA-79 |
| 文件頁數(shù)： | 35/106頁 |
| 文件大?。?/td> | 1272K |
| 代理商： | PH28F256L18T85 |
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Intel StrataFlash Wireless Memory (L18)
Datasheet
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
April 2005
35
Notes:
1.
WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to
assert either during or one data cycle before valid data.
This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is
terminated by CE# deassertion after the first word in the burst.
2.
Notes:
1.
WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during
initial latency and deasserted during valid data (RCR[10] = 0 Wait asserted low).
At the end of Word Line; the delay incurred when a burst access crosses a 16-word boundary and the
starting address is not 4-word boundary aligned.
2.
Figure 14.
Synchronous Single-Word Array or Non-array Read Timing
R312
R305
R304
R4
R17
R307
R15
R9
R7
R8
R303
R102
R3
R104
R106
R101
R105
R2
R306
R301
CLK [C]
Address [A]
ADV# [V]
CE# [E]
OE# [G]
WAIT [T]
Data [D/Q]
Figure 15.
Continuous Burst Read, showing an Output Delay Timing
R305
R305
R305
R305
R304
R4
R7
R312
R307
R15
R303
R102
R3
R106
R105
R101
R2
R304
R304
R304
R306
R302
R301
CLK [C]
Address [A]
ADV# [V]
CE# [E]
OE# [G]
WAIT [T]
Data [D/Q]
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