參數(shù)資料
型號(hào)： PH28F256L18T85
廠商： INTEL CORP
元件分類(lèi)： PROM
英文描述： StrataFlash Wireless Memory
中文描述： 16M X 16 FLASH 1.8V PROM, 85 ns, PBGA79
封裝： 0.75 MM PITCH, LEAD FREE, VFBGA-79
文件頁(yè)數(shù)： 37/106頁(yè)
文件大小： 1272K
代理商： PH28F256L18T85
Intel StrataFlash Wireless Memory (L18)
Datasheet
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
April 2005
37
7.6
AC Write Specifications
Nbr.
Symbol
Parameter
(1, 2)
Min
Max
Units
Notes
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W16
Write to Asynchronous Read Specifications
W18
t
WHAV
WE# high to Address valid
Write to Synchronous Read Specifications
W19
t
WHCH/L
WE# high to Clock valid
W20
t
WHVH
WE# high to ADV# high
Write Specifications with Clock Active
W21
t
VHWL
ADV# high to WE# low
W22
t
CHWL
Clock high to WE# low
Notes:
1.
Write timing characteristics during erase suspend are the same as write-only operations.
2.
A write operation can be terminated with either CE# or WE#.
3.
Sampled, not 100% tested.
4.
Write pulse width low (t
WLWH
or t
ELEH
) is defined from CE# or WE# low (whichever occurs last) to CE#
or WE# high (whichever occurs first). Hence, t
WLWH
= t
ELEH
= t
WLEH
= t
ELWH
.
5.
Write pulse width high (t
WHWL
or t
EHEL
) is defined from CE# or WE# high (whichever occurs first) to
CE# or WE# low (whichever occurs last). Hence, t
WHWL
= t
EHEL
= t
WHEL
= t
EHWL
).
6.
t
WHVH
or t
must be met when transitioning from a write cycle to a synchronous burst read.
7.
V
PP
and WP#
should be at a valid level until erase or program success is determined.
8.
This specification is only applicable when transitioning from a write cycle to an asynchronous read.
See spec W19 and W20 for synchronous read.
9.
When doing a Read Status operation following any command that alters the Status Register, W14 is
20 ns.
10.
Add 10ns if the write operations results in a RCR or block lock status change, for the subsequent read
operation to reflect this change.
11.
These specs are required only when the device is in a synchronous mode and clock is active during
address setup phase.
t
PHWL
t
ELWL
t
WLWH
t
DVWH
t
AVWH
t
WHEH
t
WHDX
t
WHAX
t
WHWL
t
VPWH
t
QVVL
t
QVBL
t
BHWH
t
WHGL
t
WHQV
RST# high recovery to WE# low
CE# setup to WE# low
WE# write pulse width low
Data setup to WE# high
Address setup to WE# high
CE# hold from WE# high
Data hold from WE# high
Address hold from WE# high
WE# pulse width high
V
PP
setup to WE# high
V
PP
hold from Status read
WP# hold from Status read
WP# setup to WE# high
WE# high to OE# low
WE# high to read valid
150
0
50
50
50
0
0
0
20
200
0
0
200
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,2,3
1,2,3
1,2,4
1,2
1,2,5
1,2,3,7
1,2,3,7
1,2,9
1,2,3,6,10
t
AVQV
+ 35
0
-
ns
1,2,3,6
19
19
-
-
ns
ns
1,2,3,6,10
-
-
20
20
ns
ns
1,2,3,11
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