參數(shù)資料
型號(hào)： PF48F4P0ZTQ0
廠商： Intel Corp.
元件分類： 圓形連接器
英文描述： Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT00; No. of Contacts:10; Connector Shell Size:12; Connecting Termination:Solder; Circular Shell Style:Wall Mount Receptacle
中文描述： 英特爾StrataFlash嵌入式存儲(chǔ)器
文件頁(yè)數(shù)： 55/102頁(yè)
文件大?。?/td> 1609K
代理商： PF48F4P0ZTQ0
1-Gbit P30 Family
Datasheet
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
55
10.3.1
Read Mode
The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode operation
for the device. When the RM bit is set, asynchronous page mode is selected (default). When RM is
cleared, synchronous burst mode is selected.
10.3.2
Latency Count
The Latency Count bits, LC[2:0], tell the device how many clock cycles must elapse from the
rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the first data
word is to be driven onto DQ[15:0]. The input clock frequency is used to determine this value.
Figure 28
shows the data output latency for the different settings of LC[2:0].
Synchronous burst with a Latency Count setting of Code 4 will result in zero WAIT state; however,
a Latency Count setting of Code 5 will cause 1 WAIT state (Code 6 will cause 2 WAIT states, and
Code 7 will cause 3 WAIT states) after every four words, regardless of whether a 16-word
boundary is crossed. If RCR[9] (Data Hold) bit is set (data hold of two clocks) this WAIT condition
will not occur because enough clocks elapse during each burst cycle to eliminate subsequent WAIT
states.
Refer to
Table 23, “LC and Frequency Support” on page 56
for Latency Code Settings.
3
Burst Wrap (BW)
0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]
1 =No Wrap; Burst accesses do not wrap within burst length (default)
2:0
Burst Length (BL[2:0])
001 =4-word burst
010 =8-word burst
011 =16-word burst
111 =Continuous-word burst (default)
(Other bit settings are reserved)
Note:
Latency Code 2, Data Hold for a 2-clock data cycle (DH = 1)
WAIT must be deasserted with valid data (WD =
0). Latency Code 2, Data Hold for a 2-cock data cycle (DH=1) WAIT deasserted one data cycle before valid
data (WD = 1) combination is not supported.
Table 22.
Read Configuration Register Description (Sheet 2 of 2)
相關(guān)PDF資料
PDF描述
PF48F0P0ZT00 Circular Connector; Body Material:Aluminum; Series:PT00; No. of Contacts:41; Connector Shell Size:20; Connecting Termination:Crimp; Circular Shell Style:Wall Mount Receptacle; Circular Contact Gender:Socket; Insert Arrangement:20-41
PF48F2P0ZT00 Circular Connector; No. of Contacts:41; Series:; Body Material:Aluminum; Connector Shell Size:20; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:20-41
PF48F3P0ZT00 Intel StrataFlash Embedded Memory
PF48F4P0ZT00 Circular Connector; No. of Contacts:21; Series:; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:22; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:22-21
PF48F2000P0ZBQ0 Intel StrataFlash Embedded Memory
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PF48F5000M0Y1BEA 制造商:Micron Technology Inc 功能描述:512BA/0S SCSP 1.8 X16D HF B1 ADMUX - Trays
PF48F6000M0Y0BEA 制造商:Micron Technology Inc 功能描述:1024CP/0CP SCSP 1.8 X16D LF - Trays
PF48F6000M0Y0BHA 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays
PF48F6000M0Y1BHA 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays
PF48F6600M0U0BEA 制造商:Micron Technology Inc 功能描述:1024CP/1024CP SCSP 1.8 X16D LF F1 VIRT-CE - Trays
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*