參數(shù)資料
型號： PF48F0P0VB00
廠商： Intel Corp.
英文描述： Intel StrataFlash Embedded Memory
中文描述： 英特爾StrataFlash嵌入式存儲器
文件頁數(shù)： 75/102頁
文件大?。?/td> 1609K
代理商： PF48F0P0VB00
1-Gbit P30 Family
Datasheet
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
75
14.0
Special Read States
The following sections describe non-array read states. Non-array reads can be performed in
asynchronous read or synchronous burst mode. A non-array read operation occurs as asynchronous
single-word mode. When non-array reads are performed in asynchronous page mode only the first
data is valid and all subsequent data are undefined. When a non-array read operation occurs as
synchronous burst mode, the same word of data requested will be output on successive clock edges
until the burst length requirements are satisfied.
Refer to the following waveforms for more detailed information:
Figure 16, “Asynchronous Single-Word Read (ADV# Low)” on page 38
Figure 17, “Asynchronous Single-Word Read (ADV# Latch)” on page 38
Figure 19, “Synchronous Single-Word Array or Non-array Read Timing” on page 39
14.1
Read Status Register
To read the Status Register, issue the Read Status Register command at any address. Status Register
information is available to which the Read Status Register, Word Program, or Block Erase
command was issued. Status Register data is automatically made available following a Word
Program, Block Erase, or Block Lock command sequence. Reads from the device after any of these
command sequences outputs the device’s status until another valid command is written (e.g. Read
Array command).
The Status Register is read using single asynchronous-mode or synchronous burst mode reads.
Status Register data is output on DQ[7:0], while 0x00 is output on DQ[15:8]. In asynchronous
mode the falling edge of OE#, or CE# (whichever occurs first) updates and latches the Status
Register contents. However, reading the Status Register in synchronous burst mode, CE# or ADV#
must be toggled to update status data.
The Device Write Status bit (SR[7]) provides overall status of the device. Status register bits
SR[6:1] present status and error information about the program, erase, suspend, V
PP
, and block-
locked operations.
Table 28.
Status Register Description (Sheet 1 of 2)
Status Register (SR)
Default Value = 0x80
Device
Write Status
Erase
Suspend
Status
Erase
Status
Program
Status
V
PP
Status
Program
Suspend
Status
Block-
Locked
Status
BEFP
Status
DWS
ESS
ES
PS
VPPS
PSS
BLS
BWS
7
6
5
4
3
2
1
0
Bit
Name
Description
7
Device Write Status
(DWS)
0 = Device is busy; program or erase cycle in progress; SR[0] valid.
1 = Device is ready; SR[6:1] are valid.
6
Erase Suspend Status
(ESS)
0 = Erase suspend not in effect.
1 = Erase suspend in effect.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PF48F0P0VBQ0 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory
PF48F0P0VT00 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory
PF48F0P0VTQ0 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory
PF48F0P0ZB00 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory
PF48F0P0ZBQ0 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory
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