參數(shù)資料
型號： PF38F3352LLZDQ0
廠商： INTEL CORP
元件分類： 存儲器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA88
封裝： 11 X 13 MM, SCSP-88
文件頁數(shù)： 10/54頁
文件大?。?/td> 966K
代理商： PF38F3352LLZDQ0
768-Mbit LVQ Family with Asynchronous Static RAM
18
Datasheet
4.1
Signal Descriptions
Table 2 describes the active signals used on the 768-Mbit LVQ Family with Asynchronous Static
RAM device.
Table 2.
Signal Descriptions (Sheet 1 of 3)
Symbol
Type
Description
A[MAX:MIN]
Input
ADDRESS INPUTS:
Inputs for all die addresses during read and write operations.
256-Mbit Die : AMAX= A23
128-Mbit Die : AMAX = A22
64-Mbit Die : AMAX = A21
32-Mbit Die : AMAX = A20
8-Mbit Die : AMAX = A18
A0 is the lowest-order 16-bit wide address.
A[25:24] denote high-order addresses reserved for future device densities.
D[15:0]
Input/
Output
DATA INPUTS/OUTPUTS:
Inputs data and commands during write cycles, outputs
data during read cycles. Data signals float when the device or its outputs are
deselected. Data are internally latched during writes on the flash device.
F[3:1]-CE#
Input
FLASH CHIP ENABLE:
Low-true input.
F[3:1]-CE# low selects the associated flash memory die. When asserted, flash
internal control logic, input buffers, decoders, and sense amplifiers are active. When
deasserted, the associated flash die is deselected, power is reduced to standby
levels, data and WAIT outputs are placed in high-Z state.
F1-CE# selects or deselects flash die #1; F2-CE# selects or deselects flash die #2
and is RFU on combinations with only one flash die. F3-CE# selects or deselects
flash die #3 and is RFU on stacked combinations with only one or two flash dies.
S-CS1#
S-CS2
Input
SRAM CHIP SELECT:
Low-true / high-true input (S-CS1# / S-CS2 respectively).
When either/both SRAM Chip Select signals are asserted, SRAM internal control
logic, input buffers, decoders, and sense amplifiers are active. When either/both
SRAM Chip Select signals are deasserted, the SRAM is deselected and its power is
reduced to standby levels.
S-CS1# and S-CS2 are available on stacked combinations with SRAM die and are
RFU on stacked combinations without SRAM die.
P[2:1]-CS#
Input
PSRAM CHIP SELECT:
Low-true input.
When asserted, PSRAM internal control logic, input buffers, decoders, and sense
amplifiers are active. When deasserted, the PSRAM is deselected and its power is
reduced to standby levels.
P1-CS# selects PSRAM die #1 and is available only on stacked combinations with
PSRAM die. This ball is an RFU on stacked combinations without PSRAM. P2-CS#
selects PSRAM die #2 and is available only on stacked combinations with two
PSRAM dies. This ball is an RFU on stacked combinations without PSRAM or with a
single PSRAM.
F[2:1]-OE#
Input
FLASH OUTPUT ENABLE:
Low-true input.
F[2:1]-OE# low enables the flash output buffers. F[2:1]-OE# high disables the flash
output buffers, and places the selected flash outputs in High-Z.
F1-OE# controls the outputs of flash die #1; F2-OE# controls the outputs of flash die
#2 and flash die #3. F2-OE# is available on stacked combinations with two or three
flash die and is RFU on stacked combinations with only one flash die.
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