參數(shù)資料
型號(hào)： PF38F3352LLZDQ0
廠商： INTEL CORP
元件分類： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA88
封裝： 11 X 13 MM, SCSP-88
文件頁數(shù)： 33/54頁
文件大?。?/td> 966K
代理商： PF38F3352LLZDQ0
768-Mbit LVQ Family with Asynchronous Static RAM
Datasheet
39
.
Table 14. LVQ die stacked configuration example (Top / Bottom Parameter)
17.2
Product Segment Unique Features
The code segment of the 768-Mbit LVQ Family with Asynchronous Static RAM device includes
the following enhanced features unless specifically noted otherwise:
64 unique (Intel pre-programmed) identifier bits and 2,112 user-programmable OTP bits for
each code segment flash die.
Figure 19. Top and Bottom Parameter Configurations
Code
(Top)
Data
(Bottom)
Top Parameter Partition Block Stacking
Convention
Data
(Top)
Parameter
Blocks
Main
Blocks
1-Code + 1-
Data
1-Code + 2-
Data
2-Code + 1-
Data
2-Code + 2-
Data
Code
(Top)
Code
(Top)
Code
(Top)
Code
(Top)
Code
(Bottom)
Data
(Bottom)
Data
(Bottom)
Data
(Bottom)
Data
(Top)
Data
(Top)
Code
(Bottom)
Bottom Parameter Partition Block Stacking
Convention
Parameter
Blocks
Main
Blocks
1-Code + 1-
Data
1-Code + 2-
Data
2-Code + 1-
Data
2-Code + 2-
Data
(Bottom)
Code
(Bottom)
Code
(Bottom)
Code
(Bottom)
Data
(Top)
Data
(Top)
Code
(Top)
Code
(Bottom)
Data
(Bottom)
Data
(Top)
Stacked Configuration Example (Top Parameter)
Die Stack Configuration
Flash die#1
(user selected)
Flash die #2
Flash die #3
Code only
Top
NA
Code+Data
Top
Bottom
NA
Code+Data+Data
Top
Bottom
Code+Code+Data
Top
Bottom
Stacked Configuration Example (Bottom Parameter)
Die Stack Configuration
Flash die#1
(user selected)
Flash die #2
Flash die #3
Code
Bottom
NA
Code+Data
Bottom
Top
NA
Code+Data+Data
Bottom
Top
Code+Code+Data
Bottom
Top
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