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參數(shù)資料
| 型號： | pentium III |
| 廠商： | Intel Corp. |
| 英文描述： | pentium III Processor for the PGA370 Socket at 500MHz to 933MHz(工作頻率500到933兆赫茲活動帶PGA370插孔奔III處理器) |
| 中文描述： | 奔騰III處理器在500MHz到933MHz的（工作頻率500到933兆赫茲活動帶PGA370插孔奔三處理器的PGA370插座） |
| 文件頁數(shù)： | 74/78頁 |
| 文件大?。?/td> | 610K |
| 代理商： | PENTIUM III |
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74
Datasheet
Pentium
III Processor for the PGA370 Socket at 500 MHz to 933 MHz
RSP#
I
The RSP# (Response Parity) signal is driven by the response agent (the agent
responsible for completion of the current transaction) during assertion of RS[2:0]#,
the signals for which RSP# provides parity protection. It must connect the
appropriate pins of all processor system bus agents.
A correct parity signal is high if an even number of covered signals are low and low if
an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also high,
since this indicates it is not being driven by any agent guaranteeing correct parity.
RTTCTRL
I
The RTTCTRL input signal provides AGTL+ termination control. The Pentium III
processor samples this input to sense the presence of motherboard AGTL+
termination. See the platform design guide for implementation details.
SLEWCTRL
I
The SLEWCTRL input signal provides AGTL+ slew rate control. The Pentium III
processor samples this input to determine the slew rate for AGTL+ signals when it is
the driving agent. See the platform design guide for implementation details.
SLP#
I
The SLP# (Sleep) signal, when asserted in Stop-Grant state, causes processors to
enter the Sleep state. During Sleep state, the processor stops providing internal
clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts. The processor will
recognize only assertions of the SLP#, STPCLK#, and RESET# signals while in
Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to
Stop-Grant state, restarting its internal clock signals to the bus and APIC processor
core units.
SMI#
I
The SMI# (System Management Interrupt) signal is asserted asynchronously by
system logic. On accepting a System Management Interrupt, processors save the
current state and enter System Management Mode (SMM). An SMI Acknowledge
transaction is issued, and the processor begins program execution from the SMM
handler.
STPCLK#
I
The STPCLK# (Stop Clock) signal, when asserted, causes processors to enter a low
power Stop-Grant state. The processor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock signals to all processor core units
except the bus and APIC units. The processor continues to snoop bus transactions
and latch interrupts while in Stop-Grant state. When STPCLK# is deasserted, the
processor restarts its internal clock to all units, services pending interrupts while in
the Stop-Grant state, and resumes execution. The assertion of STPCLK# has no
effect on the bus clock; STPCLK# is an asynchronous input.
TCK
I
The TCK (Test Clock) signal provides the clock input for the processor Test Bus (also
known as the Test Access Port).
TDI
I
The TDI (Test Data In) signal transfers serial test data into the processor. TDI
provides the serial input needed for JTAG specification support.
TDO
O
The TDO (Test Data Out) signal transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.
THERMDN
O
Thermal Diode Cathode. Used to calculate core (junction) temperature. See
Section
4.1
.
THERMDP
I
Thermal Diode Anode. Used to calculate core (junction) temperature. See
Section
4.1
.
THERMTRIP#
O
The processor protects itself from catastrophic overheating by use of an internal
thermal sensor. This sensor is set well above the normal operating temperature to
ensure that there are no false trips. The processor will stop all execution when the
junction temperature exceeds approximately 135 °C. This is signaled to the system
by the THERMTRIP# (Thermal Trip) pin. Once activated, the signal remains latched,
and the processor stopped, until RESET# goes active. There is no hysteresis built
into the thermal sensor itself; as long as the die temperature drops below the trip
level, a RESET# pulse will reset the processor and execution will continue. If the
temperature has not dropped below the trip level, the processor will continue to drive
THERMTRIP# and remain stopped.
TMS
I
The TMS (Test Mode Select) signal is a JTAG specification support signal used by
debug tools.
Table 33. Signal Description (Sheet 7 of 8)
Name
Type
Description
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