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參數(shù)資料
| 型號： | pentium III |
| 廠商： | Intel Corp. |
| 英文描述： | pentium III Processor for the PGA370 Socket at 500MHz to 933MHz(工作頻率500到933兆赫茲活動帶PGA370插孔奔III處理器) |
| 中文描述： | 奔騰III處理器在500MHz到933MHz的（工作頻率500到933兆赫茲活動帶PGA370插孔奔三處理器的PGA370插座） |
| 文件頁數(shù)： | 21/78頁 |
| 文件大小： | 610K |
| 代理商： | PENTIUM III |
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Datasheet
21
Pentium
III Processor for the PGA370 Socket at 500 MHz to 933 MHz
2.8.2
System Bus Frequency Select Signals (BSEL[1:0])
These signals are used to select the system bus frequency.
Table 2.9
defines the possible
combinations of the signals and the frequency associated with each combination. The frequency is
determined by the processor(s), chipset, and clock synthesizer. All system bus agents must operate
at the same frequency.
The Pentium
III
processor for the PGA370 socket operates at 100 MHz
or 133 MHz system bus frequency; 66 MHz system bus operation is not supported
. Individual
processors will only operate at their specified front side bus (FSB) frequency, either 100 MHz or
133 MHz, not both.
On motherboards that support operation at either 100 MHz or 133 MHz, the BSEL1 signal must be
pulled up to a logic high by a resistor located on the motherboard and provided as a frequency
selection signal to the clock driver/synthesizer. This signal can also be incorporated into RESET#
logic on the motherboard if only 133 MHz operation is supported (thus forcing the RESET# signal
to remain active as long as the BSEL1 signal is low.
The BSEL0 signal will float from the processor and should be pulled up to a logic high by a resistor
located on the motherboard. The BSEL0 signal can be incorporated into RESET# logic on the
motherboard if 66 MHz operation is unsupported, as demonstrated in
Figure 6
. Refer to the
appropriate clock synthesizer design guidelines and platform design guide for more details on the
bus frequency select signals.
In a 2-way MP system design, these BSEL[1:0] signals must connect the pins of both processors.
NOTES:
1. Some clock drivers may require a series resistor on their BSEL1 input.
2. Some chipsets may connect to the BSEL[1:0] signals and require a series resistor. See the appropriate
platform design guide for implementation details.
Figure 6. BSEL[1:0] Example for a 100/133 MHz or 100 MHz Only System Design
Processor
BSEL0
BSEL1
Chipset
Clock Driver
1 K
1 K
3.3V
3.3V
10 K
Note 1
10 K
Note 2
10 K
Note 2
Table 4. Frequency Select Truth Table for BSEL[1:0]
BSEL1
BSEL0
Frequency
0
0
66 MHz (unsupported)
0
1
100 MHz
1
0
Reserved
1
1
133 MHz
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