參數(shù)資料
型號： PEF3065NV3.2
廠商： SIEMENS AG
元件分類： Codec
英文描述： Signal Processing Subscriber Line Interface Codec Filter SLICOF
中文描述： 信號處理用戶線路接口編解碼器SLICOF
文件頁數(shù)： 47/102頁
文件大小： 563K
代理商： PEF3065NV3.2
PEB 3065
PEF 3065
Operating Modes
Semiconductor Group
47
01.98
6.1
The SLICOFI has 3 different reset sources that are all internally connected.
The Reset pin RES
(pin 36), which works totally asynchronous to the external clocks.
The Reset bit
(Within SOP - command, bit 4). The reset is valid for SOP-write only.
Power On Reset.
If internal
V
DDD
gets above 1.5 Volts the SLICOFI is Reset by Power
On Reset.
All 3 different sources set the SLICOFI to the basic setting modes (see below).
After a reset caused by any of the sources mentioned above, the reset bit
(SCR0-4 = RSTST) in read direction is set to one. This bit is cleared (RSTST = 0) after
it has been read by a SOP-read operation with the LSEL bits set to 00b (means: read
only SCR0 byte). A SOP-read with other LSEL bits reads the actual RSTST value, but
does not clear it.
The Reset pin RES has a Schmitt-Trigger input to reduce the sensitivity for spikes. In
addition the pin RES has a spike rejection. All spikes smaller than typ. 70 ns are
neglected. The pin RES can be set to 1 for an unlimited time but at least 125
μ
s is
recommended; during that, the DU pin is set to high impedance.
The SLICOFI leaves this mode automatically with the beginning of the next 8 kHz-frame
(or after pin RES is released).
Reset Behavior
6.2
After RESET, the SLICOFI automatically is switched to its basic settings in which it uses
internal default values for all filters and settings (AC and DC), so that the SLMA still
works in a kind of “emergency mode” and can be handled by C/I-Interface commands
only.
This means that for an (un-)determined reset (e.g. Power On Reset) the SLICOFI is
reset, but can be switched to or return automatically to any operating mode presented to
the C/I-channel after 2 FSC cycles. In all modes the SLMA stays stable, supervision and
DC-feeding are still working and conversation can go on in a proper way until all filters
and settings have been reloaded by SOP and COP-commands.
So what happens internally after reset
– all configuration registers are set to their default values (note that the Coefficient RAM
is
not
reset)
– the RSTST-bit (SCR0-4) is set to 1 to indicate that a reset has taken place
– The IOM-2 interface is reset. Running communication is stopped
– DU is in high impedance state
– AC- and DC-loop use the default values and not the programmed ones (see below)
Basic Setting Modes
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