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參數(shù)資料
| 型號： | PEF3065NV3.2 |
| 廠商： | SIEMENS AG |
| 元件分類： | Codec |
| 英文描述： | Signal Processing Subscriber Line Interface Codec Filter SLICOF |
| 中文描述： | 信號處理用戶線路接口編解碼器SLICOF |
| 文件頁數(shù)： | 35/102頁 |
| 文件大?。?/td> | 563K |
| 代理商： | PEF3065NV3.2 |
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PEB 3065
PEF 3065
Programming the SLICOFI
Semiconductor Group
35
01.98
SCR8 Configuration Register 8
Configuration register SCR8 defines some Test Mode Settings and the Ground
Key/External Indication Data Upstream Persistency Counter.
Reset value: 05
H
DCANAL
Test bit to shorten internally the IT with the
V
2W
pin
DCANAL = 0 normal operation
DCANAL = 1 the DC Analog Loop is closed
Transforms DC-Test values to 500 Hz rectangular values at the PCM
interface
CHOPACT = 0
normal operation
CHOPACT = 1
chopping function is activated
Holds the actual DC-value at the
V
2W
output
DCHOLD = 0 normal operation
DCHOLD = 1 hold DC-value at V2W
External Masterclock (16 MHz)
EXT_MCLK1 = 0 internal masterclock is used
EXT_MCLK1 = 1 external masterclock is used
To use an external masterclock of 16 MHz following steps must be done:
1. IO1 must be set to input and becomes the input-pin of the
masterclock (
page
42
)
2. Connect the internal clockline to IO1 and disable the PLL by setting
the bit EXT_MCLK1 = 1
To restrict the rate of upstream C/I-bit changes, deglitching (persistence
checking) of the status information from the SLICOFI may be applied.
New status information will be transmitted upstream, after it has been
stable for N milliseconds. N is binary programmable in the range of 4 to
60 ms in steps of 4 ms, with DUPGNK = 0h the deglitching is disabled.
Reset value is 20 ms.
The HOOK bit (for external Indication) and the GNK bit are influenced.
Detailed info see
chapter 5.6
.
CHOPACT
DCHOLD
EXT_MCLK1
DUPGNK
Bit
7
6
5
4
3
2
1
0
DCANAL
CHOPACT
DCHOLD
EXT_MCLK 1
DUPGNK3
DUPGNK2
DUPGNK1
DUPGNK0
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