參數(shù)資料
型號: PEB2466-HV1.2
廠商: SIEMENS A G
元件分類: 編解碼器
英文描述: Four Channel Codec Filter with PCM- and m-Controller Interface SICOFI4-mC
中文描述: A/MU-LAW, PCM CODEC, PQFP64
文件頁數(shù): 55/82頁
文件大?。?/td> 3330K
代理商: PEB2466-HV1.2
PEB 2466
Transmission Characteristics
Semiconductor Group
55
02.97
4
The figures in this specification are based on the subscriber-line board requirements.
The proper adjustment of the programmable filters (transhybrid balancing, impedance
matching, frequency-response correction) requires a complete knowledge of the
μ
C-SICOFI-4’s analog environment. Unless otherwise stated, the transmission
characteristics are guaranteed within the test conditions.
Transmission Characteristics
Test Conditions
T
A
= 0 °C to 70 °C;
V
DD
= 5 V
±
5%; GNDA1..4 = GNDD = 0 V
R
L
HPR and HPX enabled;
AR
2)
= 0 to – 9 dB
AX
3)
= 0 to 9 dB for A-Law, 0 to 7 dB for
μ
-Law
f
= 1014 Hz; 0 dBm0; A-Law or
μ
-Law;
AGX = 0 dB, 6.02 dB, AGR = 0 dB, – 6.02dB;
1)
> 300
;
C
L
< 50 pF; H(IM) = H(TH) = 0; H(R1) = H(FRX) = H(FRR) = 1;
A-Law
A 0 dBm0
signal is equivalent to 1.095 Vrms. A + 3.14 dBm0 signal is equivalent to
1.57 Vrms which corresponds to the overload point of 2.223 V.
When the gain in the receive path is set at 0 dB, an 1014 Hz PCM sinewave input with
a level 0 dBm0 will correspond to a voltage of 1.095 Vrms at the analog output.
When the gain in the transmit path is set at 0 dB, an 1014 Hz sine wave signal with a
voltage of 1.095Vrms A-Law will correspond to a level of 0 dBm0 at the PCM output.
μ
-Law
In transmit direction for
μ
-law an additional gain of 1.94 dB is implemented automatically,
in the companding block (CMP). This additional gain has to be considered at all gain
calculations, and reduces possible AX-gain from 9 dB (with A-Law) to 7 dB (with
μ
-Law)
A 0 dBm0
4)
signal is equivalent to 1.0906 Vrms. A + 3.17 dBm0 signal is equivalent to
1.57 Vrms which corresponds to the overload point of 2.223 V.
When the gain in the receive path is set at 0 dB, an 1014 Hz PCM sinewave input with
a level 0 dBm0 will correspond to a voltage of 1.0906 Vrms at the analog output.
When the gain in the transmit path is set at 0 dB, an 1014 Hz sine wave signal with a
voltage of 1.0906 Vrms will correspond to a level of 1.94 dBm0 at the PCM output.
1)
R
,
C
forms the load on VOUT
2)
Consider, in a complete system, AR = AR1 + AR2 + FRR + R1
3)
Consider, in a complete system, AX = AX1 + AX2 + FRX
4)
The absolute power level in decibels referred to (a point of zero relative level) the PCM interface levels.
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