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參數(shù)資料
| 型號： | PEB2466-HV1.2 |
| 廠商： | SIEMENS A G |
| 元件分類： | 編解碼器 |
| 英文描述： | Four Channel Codec Filter with PCM- and m-Controller Interface SICOFI4-mC |
| 中文描述： | A/MU-LAW, PCM CODEC, PQFP64 |
| 文件頁數(shù)： | 47/82頁 |
| 文件大?。?/td> | 3330K |
| 代理商： | PEB2466-HV1.2 |
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PEB 2466
Programming the SICOFI
-4-
μ
C
Semiconductor Group
47
02.97
3.5.7
This register configures the operation of the PCM-interface
XR6 Extended Register 6
Bit 7
0
C-MODE
X-S
R-S
DRV_0
Shift
PCM-OFFSET
C-MODE
Defines the CLK-Mode for the PCM-interface
C-Mode = 0:
Single clocking is used
C-Mode = 1:
Double clocking is used
X-S
Transmit Slope
X-S = 0:
X-S = 1:
Transmission starts with rising edge
Transmission starts with falling edge
R-S
Receive Slope
R-S= 0:
R-S= 1:
Data is sampled with falling edge of PCLK
Data is sampled with rising edge of PCLK
DRV_0
Driving Mode for Bit 0 (only available with single clocking mode)
DRV_0 = 0:
Bit 0 is driven the whole PCLK-period
DRV_0 = 1:
Bit 0 is driven during the first half of the
PCLK-period only
Shift
Shifts the access to DXA/B and DRA/B for one PCLK-period
(only available with double clocking mode)
Shift = 0:
No shift takes place
Shift = 1:
Access to DXA/B and DRA/B is shifted for one
PCLK-per.
PCM-OFFSET
Offset in number of data-clock periods added to Time slot
0 0 0:
No offset is added
0 0 1:
One data clock period is added
...
1 1 1
Seven data clock periods are added
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PEB2466HV2.2 | 功能描述:接口—CODEC POTS RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| PEB2466-HV2.2 | 制造商:Infineon Technologies AG 功能描述:PCM CODEC, Quad, 64 Pin, Plastic, QFP |
| PEB2466HV2.2/TR | 制造商:Lantiq 功能描述: |
| PEB2466HV2.2TR | 制造商:Rochester Electronics LLC 功能描述: 制造商:Infineon Technologies AG 功能描述: |
| PEB2466HV22XP | 制造商:Lantiq 功能描述:ICS FOR COMMUNICATIONS |
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