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參數(shù)資料
| 型號(hào)： | PEB2445-N |
| 廠(chǎng)商： | SIEMENS A G |
| 元件分類(lèi)： | 路由/交換 |
| 英文描述： | Multipoint Switching and Conferencing Unit - Attenuation MUSAC-A |
| 中文描述： | TELECOM, CONFERENCING CIRCUIT, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 41/70頁(yè) |
| 文件大?。?/td> | 1236K |
| 代理商： | PEB2445-N |
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PEB 2445
Detailed Register Description
Semiconductor Group
41
02.96
4
The following registers may be accessed:
Detailed Register Description
Table 6
Addressing the Direct Registers
If A1 is not connected it is internally set to ground. In the demultiplexed mode neither an
access to the CMR, CST nor a read access to the MOD register is possible.
The paragraphs in this section cover the registers in detail.
4.1
Access in the multiplexed
μ
P-interface mode:
Access in the demultiplexed
μ
P-interface mode: Write, address: 0
H
read, address: 0
H
Reset value: BF
H
Mode Register (MOD)
Write, address: 0
H
read, address: 6
H
RC
Reset Connection
memory; writing a zero to this bit causes the complete
connection memory to be overwritten with 200
H
(tristate). During this time
STA:B is set. The maximum time for resetting is 250
μ
s.
Reset Indirect
access mechanism; setting this bit resets the indirect access
mechanism. Rl has to be cleared before writing/reading IAR after reset.
Stand By
; By selecting SB = 1 all PCM outputs are tristated. The connection
memory works normally. The MUSAC-A can be activated immediately by
resetting SB.
Input/Output
operation
Mode
; these bits define the bit rate of the input and
output lines. The bitrates are given in
table 7
, the corresponding pin functions
in
table 8
(standard configuration).
RI
SB
MI1/0
MO1/0
Address
Write Operation
Read Operation
Demultiplexed Mode
A(1:0)
0
H
1
H
2
H
3
H
Multiplexed Mode
AD(7:0)
0
H
2
H
4
H
6
H
MOD
IAR
CMR
–
STA
IAR
CST
MOD
AD7
AD0
RC
0
RI
SB
MI1
MI0
MO1
MO0
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