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參數(shù)資料
| 型號(hào)： | PEB2445-N |
| 廠商： | SIEMENS A G |
| 元件分類： | 路由/交換 |
| 英文描述： | Multipoint Switching and Conferencing Unit - Attenuation MUSAC-A |
| 中文描述： | TELECOM, CONFERENCING CIRCUIT, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 37/70頁 |
| 文件大?。?/td> | 1236K |
| 代理商： | PEB2445-N |
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PEB 2445
Functional Description
Semiconductor Group
37
02.96
Indirect access to the CFR, CSR, CM or CCM:
An indirect access is performed by reading/writing three consecutive bytes (first byte =
control byte, second byte = data byte, third byte = address byte) to/from IAR.
The control byte determines whether the CFR, the CSR, the CM or the CCM shall be
accessed, whether a write or read operation shall be performed and whether the first or
the second memory access shall be executed. (To describe a conference two accesses
to the CCM are necessary). The bits D7
…
D0 contain the information which shall be
written into the control memories or the indirect registers. In the case of programming
the CM the output attenuation is included either in the control byte (transparent switch)
or in the data bits (conference switch). The address byte indicates which one of the
indirect registers shall be accessed or in which memory location the data shall be written.
An exact definition is given in
chapter 4.5
.
Before an indirect access is started, the Z- and B bits of the status register must be 0.
With the first instruction the Z bit is set (see
chapter 4.2
). After the third instruction the
MUSAC-A accesses the memory location. This access requires maximally 900 ns. After
the access is finished the Z bit is reset.
Figure 17 a)
illustrates a write operation on the IAR.
It is possible to read or write the direct access registers while an indirect access is in
progress. Thus a register may be read in the time intervals that separate the three
sequential indirect access instructions. Also, the current indirect access may be aborted
by setting the MOD:RI. One indirect register access has to be completed before the next
one can be started.
To read the indirect registers or the CM two sequences of three instructions each have
to be programmed. In the first sequence the MUSAC-A is instructed which register or CM
address to read. The data transferred to the PEB 2445 in this first sequence is of no
significance. With the first write instruction STA:Z is set. After the first 3 instructions the
MUSAC-A needs 900 ns to write the result to the IAR. The status register bit Z is reset
after maximally 900 ns. Then 3 read operations follow. Again, STA:Z is set with the first
read instruction. The 3 instructions read 3 bytes from the IAR.
Figure 17 b)
shows this
procedure. After the third read operation the PEB 2445 needs another 900 ns to reset
the indirect access mechanism and the Z bit in the status register. In CCM read accesses
three sequences of three instructions (two identical write sequences and one read
sequence; see
figure 17 c)
are necessary.
Bit 7
Bit 0
D8
D0
IA0
C3
D7
IA7
C2
D6
IA6
K1
D5
IA5
K0
D4
IA4
C1
D3
IA3
C0
D2
IA2
D9
D1
IA1
Control Byte
Data Byte
Address Byte
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相關(guān)代理商/技術(shù)參數(shù) |
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| PEB2447H-V12 | 功能描述:IC SWITCH MEM TIME CMOS 100-MQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:* 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
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