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PEB 20321
PEF 20321
Local Bus Interface (LBI)
Data Sheet
150
2001-02-14
6.2
LBI External Bus Controller (EBC)
The External Bus Controller (EBC) provides a flexible bus interface to connect a wide
range of peripherals. In normal mode, this interface is master and drives peripheral
devices. It provides the ability to select busses of different configuration: 8 bit
multiplexed/de-multiplexed or 16 bit multiplexed/de-multiplexed. The configurable pins
of DMA support/General Purpose Bus provide alternate functionality to support the LBI
pins.
The EBC performs
‘
funneling
’
of data to or from the LBI FIFOs (as DWORDs) to the 8-/
16-bit LBI bus. The EBC also supports bus arbitration. It inter-works with all other blocks
of the LBI (FIFOs, DMSM and Mailbox registers), as well as supporting a
‘
Direct Access
’
path to the internal bus. It also provides the de-multiplexed address lines on the LBI
address pins, if the MUNICH32X is operated in de-multiplexed mode.
The function of the EBC is controlled via the LBI Configuration register LCONF. It
specifies the external bus cycles in terms of address (multiplexed/de-multiplexed), data
(16-bit/8-bit) and control signal length (wait states).
6.2.1
External Bus Modes
Multiplexed Bus Modes
In the 16-bit multiplexed bus mode both the address and data lines use the pins
LD(15:0). The address is time-multiplexed with the data and has to be latched externally.
The width of the required latch depends on the selected data bus width, i.e. an 8-bit data
bus requires a byte latch (the address bits LD15
…
LD8 on the LBI port do not change,
while on LD7
…
LD0 address and data are multiplexed), a 16-bit data bus requires a
word latch (the least significant address line LA0 is not relevant for word accesses).
In de-multiplexed mode, the address lines are permanently output on pins LA(15:0) and
do not require latches.
The EBC initiates an external access by generating the Address Latch Enable signal
(LALE) and then placing an address on the bus. The falling edge of LALE triggers an
external latch to capture the address. After a period of time during which the address
must have been latched externally, the address is removed from the bus. The EBC now
activates the respective command signal (LRD, LWR, LBHE). Data is driven onto the bus
either by the EBC (for write cycles) or by the external memory/peripheral (for read
cycles). After a period of time, which is determined by the access time of the memory/
peripheral, data become valid.
Read cycles:
Input data is latched and the command signal is now deactivated. This
causes the accessed device to remove its data from the bus which is then tri-stated
again.
Write cycles:
The command signal is now deactivated. The data remain valid on the bus
until the next external bus cycle is started.