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參數(shù)資料
| 型號(hào)： | PE3236-54 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, PQCC44 |
| 封裝： | GREEN, PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 3/15頁(yè) |
| 文件大?。?/td> | 456K |
| 代理商： | PE3236-54 |
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Product Specification
PE3236
Page 11 of 15
Document No. 70-0026-04
│ www.psemi.com
2003-2010 Peregrine Semiconductor Corp. All rights reserved.
A lock detect output, LD is also provided, via the
pin Cext. Cext is the logical “NAND” of PD_U and
PD_D waveforms, which is driven through a series
2 k
resistor. Connecting Cext to an external
shunt capacitor provides integration. Cext also
drives the input of an internal inverting comparator
with an open drain output. Thus LD is an “AND”
function of PD_U and PD_D.
Enhancement Register
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 9. Enhancement Register Bit Functionality
** Program to 0
Phase Detector
The phase detector is triggered by rising edges
from the main Counter (fp) and the reference
counter (fc). It has two outputs, namely PD_U,
and PD_D. If the divided VCO leads the divided
reference in phase or frequency (fp leads fc),
PD_D pulses “l(fā)ow”. If the divided reference leads
the divided VCO in phase or frequency (fc leads
fp), PD_U pulses “l(fā)ow”. The width of either pulse
is directly proportional to phase offset between the
two input signals, fp and fc.
PD_U and PD_D drive an active loop filter which
controls the VCO tune voltage. PD_U pulses
result in an increase in VCO frequency and PD_D
results in a decrease in VCO frequency.
Bit Function
Description
Bit 0
Reserved**
Bit 1
Reserved**
Bit 2
Reserved**
Bit 3
Power down
Power down of all functions except programming interface.
Bit 4
Counter load
Immediate and continuous load of counter programming as directed by the Bmode and Smode inputs.
Bit 5
MSEL output
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.
Bit 6
Prescaler output
Drives the raw internal prescaler output onto the Dout output.
Bit 7
fp, fc OE
fp, fc outputs disabled.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PE3236-21 | PHASE LOCKED LOOP, PQCC44 |
| PE33361MLIAA-Z | PHASE LOCKED LOOP, QCC48 |
| PE33361MLIAA | PHASE LOCKED LOOP, QCC48 |
| PE3337-99 | PHASE LOCKED LOOP, UUC52 |
| PE33631MLIAA | PHASE DETECTOR, QCC64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PE3236EK | 制造商:PEREGRINE 制造商全稱:PEREGRINE 功能描述:2200 MHz UltraCMOS-TM Integer-N PLL for Low Phase Noise Applications |
| PE3238 | 制造商:PEREGRINE 制造商全稱:PEREGRINE 功能描述:1500 MHz UltraCMOS⑩ Integer-N PLL for Low Phase Noise Applications |
| PE3238EK | 制造商:PEREGRINE 制造商全稱:PEREGRINE 功能描述:1500 MHz UltraCMOS? Integer-N PLL for Low Phase Noise Applications |
| PE3238LF | 制造商:PASTERNACK 制造商全稱:Pasternack Enterprises, Inc. 功能描述:CABLE ASSEMBLY RG223/U BNC MALE TO SMC PLUG |
| PE3239 | 制造商:PEREGRINE 制造商全稱:PEREGRINE 功能描述:2.2 GHz Integer-N PLL for Low Phase Noise Applications |
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