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參數(shù)資料
| 型號(hào)： | PDM4M3120S12M |
| 廠商： | IXYS CORP |
| 元件分類： | SRAM |
| 英文描述： | 1M X 32 MULTI DEVICE SRAM MODULE, 12 ns, SMA72 |
| 封裝： | SIMM-72 |
| 文件頁(yè)數(shù)： | 6/10頁(yè) |
| 文件大?。?/td> | 108K |
| 代理商： | PDM4M3120S12M |
PDM4M3120
6
Rev 1.1
PRELIMINARY
AC Electrical Characteristics
(Vcc = 3.3V
±
10%, T
A
= 0
°
C to +70
°
C)
NOTE
1. This parameter is determined by device characteristics but is not production tested.
Symbol
Parameter
PDM4M3120SXXZ, PDM4M3120SXXM
Unit
-20 ns
-15 ns
-12 ns
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
20
—
15
—
12
—
ns
t
AA
Address Access Time
—
20
—
15
—
12
ns
t
ACS
t
CLZ(1)
Chip Select Access Time
—
20
—
15
—
12
ns
Chip Select to Output inLow-Z
3
—
3
—
3
—
ns
t
OE
t
OLZ(1)
t
CHZ(1)
t
OHZ(1)
Output Enable to Output Valid
—
10
—
8
—
7
ns
Output Enable to Output in Low-Z
0
—
0
—
0
—
ns
Chip Deselect to Output in High-Z
—
7
—
7
—
7
ns
Output Disable to Output in High-Z
—
7
—
7
—
7
ns
t
OH
t
PU(1)
t
PD(1)
Output Hold from Address Change
3
—
3
—
3
—
ns
Chip Select to Power-Up Time
0
—
0
—
0
—
ns
Chip Deselect to Power-Down Time
—
20
—
15
—
12
ns
Write Cycle
t
WC
Write Cycle Time
20
—
15
—
12
—
ns
t
CW
Chip Select to End of Write
12
—
10
—
10
—
ns
t
AW
Address Valid to End of Write
12
—
10
—
10
—
ns
t
AS
Address Setup Time
0
–
0
—
0
—
ns
t
WP
Write Pulse Width
15
—
13
—
12
—
ns
t
WR
t
WHZ(1)
Write Recovery Time
3
—
3
—
3
—
ns
Write Enable to Output in High-Z
—
7
—
7
—
7
ns
t
DW
Data to Write Time Overlap
12
—
10
—
10
—
ns
t
DH
t
OW(1)
Data Hold from Write Time
0
—
0
—
0
—
ns
Output Active from End of Write
0
—
0
—
0
—
ns
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