參數(shù)資料
型號(hào): PDM4M3120S12M
廠商: IXYS CORP
元件分類: SRAM
英文描述: 1M X 32 MULTI DEVICE SRAM MODULE, 12 ns, SMA72
封裝: SIMM-72
文件頁數(shù): 1/10頁
文件大小: 108K
代理商: PDM4M3120S12M
Rev 1.1
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PRELIMINARY
Features
n
High-density 3.3V, 4 megabyte Static RAM
module
Low profile 72-pin ZIP (Zig-zag In-line vertical
Package) or 72-pin SIMM or Angled SIMM
(Single In-line Memory Module)
Fast access time: 12 ns (max.)
Surface mounted plastic components on an
epoxy laminate (FR-4) substrate.
Single 3.3V (
±
10%) power supply
Multiple V
SS
pins and decoupling capacitors for
maximum noise immunity
Inputs/ outputs directly TTL compatible
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Description
The PDM4M3120 is a 3.3V, 1M x 32 static RAM
module constructed on an epoxy laminate (FR-4)
substrate using eight 1M x 4 static RAMs in plastic
SOJ packages. Availability of four chip select lines
(one for each of four RAMs) provides byte access.
The PDM4M3120 is available with access times as
fast as 12 ns with minimal power consumption.
The PDM4M3120 is packaged in a 72-pin FR-4 ZIP
(Zig-zag In-line vertical Package) or a 72-pin SIMM or
Angled SIMM (Single In-line Memory Module). The
ZIP configuration allows 72 pins to be placed on a
package 3.950" long and 0.365" wide. At only 0.590"
high, this low-profile package is ideal for systems
with minimum board spacing. The SIMM configura-
tion allows use of edge mounted sockets to secure the
module.
All inputs and outputs of the PDM4M3120 are TTL
compatible and operate from a single 3.3V supply.
Full asynchronous circuitry requires no clock or
refresh for operation and provides equal access and
cycle times for ease of use.
Four identification pins (PD0, PD1, PD2, PD3) are pro-
vided for applications in which different density
versions of the module are used. In this way, the tar-
get system can read the respective levels of PD0, PD1,
PD2, PD3 to determine a 1M depth.
PDM4M3120
3.3V, 1M x 32 CMOS
Static RAM Module
Functional Block Diagram
I/O31-I/O0
8
8
8
8
CS
1
CS
2
CS
3
CS
4
20
4
ADDRESS
WE
OE
PD3-PD0
1M x 32
RAM
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