參數(shù)資料
型號(hào)： PDI1394P23EC
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 2-port/1-port 400 Mbps physical layer interface
中文描述： 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PBGA64
封裝： 8 X 8 X 1.05 MM, PLASTIC, LFBGA-64
文件頁(yè)數(shù)： 19/42頁(yè)
文件大?。?/td> 233K
代理商： PDI1394P23EC
Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2001 Sep 06
19
Table 8. Page 7 (Vendor-Dependent) Register Field Descriptions
FIELD
SIZE
2
TYPE
Rd/Wr
DESCRIPTION
Link_Speed
Link speed. This field indicates the top speed capability of the attached LLC. Encoding is as follows:
Code
Speed
00
S100
01
S200
10
S400
11
illegal
This field is replicated in the “sp” field of the self-ID packet to indicate the speed capability of the node
(PHY and LLC in combination). However, this field does not affect the PHY speed capability indicated to
peer PHYs during self-ID; the PDI1394P23 PHY identifies itself as S400 capable to its peers regardless
of the value in this field. This field is set to 10b (S400) by hardware reset and is unaffected by bus-reset.
An 11b can be written into this field, however, a 10b will be sent in the self-ID packet.
Bridge_Aware
2
Rd/Wr
Bridge_Aware. This field reports Bridge_Aware capability to all nodes via the self-ID packet. Encoding
is as follows:
Code
Meaning
00
Non-bridge device
01
Reserved (BRAN Bridge)
10
Bridge compliant with 1394.1 (unchanged state)
11
Bridge compliant with 1394.1 (changed state)
This field is replicated in bits 18 and 19 of the self-ID packet. The value of this field does not affect PHY
operation. It is a reporting mechanism. The default value for this field is set by the BRIDGE pin. The
BRIDGE pin is sampled during a hardware reset (RESET low). When the BRIDGE pin is low, this field
is set to “00” indicating a “non-bridge device.” When the BRIDGE pin is high, this field is set to “11”
indicating a “1394.1 bridge compliant” device. Writing to this field overrides the default setting by the
BRIDGE pin.
相關(guān)PDF資料
PDF描述
PDI1394L40 1394 enhanced AV link layer controller
PDI1394L40BE 8349 TBGA NO PB W/O ENC
PDI1394P11 3-port physical layer interface
PDI1394P11BD 3-port physical layer interface
PDI1394P25 1-port 400 Mbps physical layer interface
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PDI1394P24BD 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LINE TRANSCEIVER|CMOS|4 DRIVER|4 RCVR|QFP|64PIN|PLASTIC
PDI1394P25 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1-port 400 Mbps physical layer interface
PDI1394P25BD 功能描述:輸入/輸出控制器接口集成電路 1394 1 PORT 400 MB/S PHY RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
PDI1394P25BD,118 制造商:NXP Semiconductors 功能描述:1394 1 PORT 400 MB/S PHY - Tape and Reel
PDI1394P25BD,151 制造商:NXP Semiconductors 功能描述:1394 1 PORT 400 MB/S PHY - Trays
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*