參數(shù)資料
型號(hào)： PDI1394P23EC
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 2-port/1-port 400 Mbps physical layer interface
中文描述： 2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PBGA64
封裝： 8 X 8 X 1.05 MM, PLASTIC, LFBGA-64
文件頁數(shù)： 11/42頁
文件大小： 233K
代理商： PDI1394P23EC
Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2001 Sep 06
11
9.0
SYMBOL
RECOMMENDED OPERATING CONDITIONS
PARAMETER
CONDITION
MIN
3.0
2.7
1
2.3
2.6
TYP
3.3
3.0
—
—
MAX
3.6
3.6
—
—
UNIT
V
V
V
V
V
DD
Supply voltage
Source power node
Non-source power node
ISO = V
DD
, V
DD
>= 2.7 V
ISO = V
DD
, V
DD
>= 3.0 V
High-level input voltag
CTL0, CTL1, D0-D7
V
IH
High-level input voltage, C/LKON
2
,
PC0–PC2, ISO, PD
High-level input voltage, RESET
Low-level input voltage, LREQ,
CTL0, CTL1, D0–D7
Low-level input voltage, C/LKON
2
,
PC0–PC2, ISO, PD,
Low-level input voltage, RESET
Output current
0.7 V
DD
—
—
V
0.6 V
DD
—
—
—
ISO = V
DD
—
—
0.7
V
V
IL
—
—
0.2 V
DD
V
—
–6
118
168
1.165
1.165
0.935
0.935
0.523
0.523
2
—
—
—
—
—
—
—
0.3 V
DD
2.5
260
265
2.515
2.015
1
2.515
2.015
1
2.515
2.015
1
—
1.08
0.5
0.315
0.8
0.55
0.5
—
mA
mV
mV
V
V
V
V
V
V
ms
ns
ns
ns
ns
ns
ns
I
O
TPBIAS outputs
TPA, TPB cable inputs, during data reception
TPA, TPB cable inputs, during data arbitration
V
ID
Differential input voltage amplitude
Differential in ut voltage am litude
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IC 100
V
IC-100
TPB common-mode input voltage
TPB common-mode in ut voltage
Speed signaling off
or S100 speed signal
Source power node
Non-source power node
Source power node
Non-source power node
Source power node
Non-source power node
IC 200
V
IC-200
TPB common-mode input voltage
TPB common-mode in ut voltage
S200 speed signal
S200 s eed signal
IC 400
V
IC-400
TPB common-mode input voltage
TPB common-mode in ut voltage
S400 speed signal
S400 s eed signal
t
PU
Power-up reset time
Set by capacitor between RESET pin and GND
TPA, TPB cable inputs, S100 operation
TPA, TPB cable inputs, S200 operation
TPA, TPB cable inputs, S400 operation
Between TPA and TPB cable inputs, S100 operation
Between TPA and TPB cable inputs, S200 operation
Between TPA and TPB cable inputs, S400 operation
Crystal connected according to Figure 10 or external
clock input at pin XI
Receive input jitter
Receive input skew
f
XTAL
Crystal or external clock frequency
24.5735
24.576
24.5785
MHz
NOTES:
1. For a node that does not source power to the bus (see Section 4.2.2.2 in the IEEE 1394-1995 standard).
2. C/LKON is only an input when RESET = 0.
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