- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369960 > PDI1394P21BE (NXP SEMICONDUCTORS) 3-port physical layer interface PDF資料下載
參數(shù)資料
| 型號： | PDI1394P21BE |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3-port physical layer interface |
| 中文描述： | 3 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件頁數(shù)： | 37/42頁 |
| 文件大?。?/td> | 233K |
| 代理商： | PDI1394P21BE |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁當前第37頁第38頁第39頁第40頁第41頁第42頁
Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2001 Sep 06
37
The sequence of events for disabling the PHY-LLC interface when it
is in the non-differentiated mode of operation (ISO terminal is high)
is as follows:
1. Normal operation. Interface is operating normally, with LPS
active, SYSCLK active, status and packet data reception and
transmission via the CTL and D lines, and request activity via
the LREQ line.
2. LPS deasserted. The LLC deasserts the LPS signal and, within
1.0 ms, terminates any request or interface bus activity, places
its CTL and D outputs into a high-impedance state, and drives
its LREQ output low.
3. Interface reset. After T
LPS_RESET
time, the PHY determines that
LPS is inactive, terminates any interface bus activity, and drives
its CTL and D outputs low. The PHY-LLC interface is now in the
reset state.
4. Interface disabled. If the LPS signal remain inactive for
T
LPS_DISABLE
time, the PHY terminates SYSCLK activity by
driving the SYSCLK output low. The PHY-LLC interface is now in
the disabled state.
After the interface has been reset, or reset and then disabled, the
interface is initialized and restored to normal operation when LPS is
reasserted by the LLC. The timing for interface initialization is shown
in Figure 24 and Figure 25.
T
CLK_ACTIVATE
CTL0
LPS
SV01814
ISO
SYSCLK
D0 – D7
LREQ
(low)
(c)
7 cycles
5 ns. min
10 ns. max
(d)
(b)
CTL1
(a)
Figure 24.
Interface Initialization, ISO Low
相關PDF資料 |
PDF描述 |
|---|---|
| PDI1394P22BD | 3-port physical layer interface |
| PDI1394L11BA | 1394 AV link layer controller |
| PDI1394L21BE | 1394 full duplex AV link layer controller |
| PDI1394L21BP | 1394 full duplex AV link layer controller |
| PDL-TTL-7-1 | Programmable Delay Line |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PDI1394P22 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3-port physical layer interface |
| PDI1394P22BD | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3-port physical layer interface |
| PDI1394P23 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2-port/1-port 400 Mbps physical layer interface |
| PDI1394P23BD | 功能描述:IC IEEE 1394 LINK CTRLR 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應商設備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| PDI1394P23BD,118 | 功能描述:輸入/輸出控制器接口集成電路 1394 2-PORT PHY NO NEW DESIGNS RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復。