參數(shù)資料
型號: PDI1394P21BE
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 3-port physical layer interface
中文描述: 3 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP80
封裝: 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80
文件頁數(shù): 36/42頁
文件大?。?/td> 233K
代理商: PDI1394P21BE
Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2001 Sep 06
36
The sequence of events for disabling the PHY-LLC interface when it
is in the differentiated mode of operation (ISO terminal is low) is as
follows:
1. Normal operation. Interface is operating normally, with LPS
active, SYSCLK active, status and packet data reception and
transmission via the CTL and D lines, and request activity via
the LREQ line.
2. LPS deasserted. The LLC deasserts the LPS signal and, within 1
ms, terminates any request or interface bus activity, and places
its LREQ, CTL, and D outputs into a high-impedance state (the
LLC should terminate any output signal activity such that signals
end in a logic 0 state).
3. Interface reset. After T
LPS_RESET
time, the PHY determines that
LPS is inactive, terminates any interface bus activity, and places
its CTL and D outputs into a high-impedance state (the PHY will
terminate any output signal activity such that signals end in a
logic 0 state). The PHY-LLC interface is now in the reset state.
4. Interface disabled. If the LPS signal remain inactive for
T
LPS_DISABLE
time, the PHY terminates SYSCLK activity by
placing the SYSCLK output into a high-impedance state. The
PHY-LLC interface is now in the disabled state.
T
LPS_RESET
T
LPS_DISABLE
CTL0, CTL1
LPS
SV01813
ISO
SYSCLK
D0 – D7
LREQ
(high)
(a)
(c)
(b)
(d)
Figure 23.
Interface Disable, ISO High
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相關代理商/技術參數(shù)
參數(shù)描述
PDI1394P22 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3-port physical layer interface
PDI1394P22BD 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3-port physical layer interface
PDI1394P23 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2-port/1-port 400 Mbps physical layer interface
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