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參數(shù)資料
| 型號： | PDI1394P21BE |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3-port physical layer interface |
| 中文描述： | 3 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件頁數(shù)： | 19/42頁 |
| 文件大?。?/td> | 233K |
| 代理商： | PDI1394P21BE |
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Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2001 Sep 06
19
Table 8. Page 7 (Vendor-Dependent) Register Field Descriptions
FIELD
SIZE
2
TYPE
Rd/Wr
DESCRIPTION
Link_Speed
Link speed. This field indicates the top speed capability of the attached LLC. Encoding is as follows:
Code
Speed
00
S100
01
S200
10
S400
11
illegal
This field is replicated in the “sp” field of the self-ID packet to indicate the speed capability of the node
(PHY and LLC in combination). However, this field does not affect the PHY speed capability indicated to
peer PHYs during self-ID; the PDI1394P23 PHY identifies itself as S400 capable to its peers regardless
of the value in this field. This field is set to 10b (S400) by hardware reset and is unaffected by bus-reset.
An 11b can be written into this field, however, a 10b will be sent in the self-ID packet.
Bridge_Aware
2
Rd/Wr
Bridge_Aware. This field reports Bridge_Aware capability to all nodes via the self-ID packet. Encoding
is as follows:
Code
Meaning
00
Non-bridge device
01
Reserved (BRAN Bridge)
10
Bridge compliant with 1394.1 (unchanged state)
11
Bridge compliant with 1394.1 (changed state)
This field is replicated in bits 18 and 19 of the self-ID packet. The value of this field does not affect PHY
operation. It is a reporting mechanism. The default value for this field is set by the BRIDGE pin. The
BRIDGE pin is sampled during a hardware reset (RESET low). When the BRIDGE pin is low, this field
is set to “00” indicating a “non-bridge device.” When the BRIDGE pin is high, this field is set to “11”
indicating a “1394.1 bridge compliant” device. Writing to this field overrides the default setting by the
BRIDGE pin.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PDI1394P22BD | 3-port physical layer interface |
| PDI1394L11BA | 1394 AV link layer controller |
| PDI1394L21BE | 1394 full duplex AV link layer controller |
| PDI1394L21BP | 1394 full duplex AV link layer controller |
| PDL-TTL-7-1 | Programmable Delay Line |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDI1394P22 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3-port physical layer interface |
| PDI1394P22BD | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3-port physical layer interface |
| PDI1394P23 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2-port/1-port 400 Mbps physical layer interface |
| PDI1394P23BD | 功能描述:IC IEEE 1394 LINK CTRLR 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| PDI1394P23BD,118 | 功能描述:輸入/輸出控制器接口集成電路 1394 2-PORT PHY NO NEW DESIGNS RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
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