參數(shù)資料
型號(hào)： PDI1394L41BE
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8358 PBGA ENCRP NO-PB
中文描述： 1 CHANNEL(S), 400M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： PLASTIC, QFP-144
文件頁(yè)數(shù)： 6/42頁(yè)
文件大?。?/td> 233K
代理商： PDI1394L41BE
Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2001 Sep 06
6
Name
Description
I/O
LFBGA
Ball
Numbers
LQFP
Pin
Numbers
Pin Type
CTL0,
CTL1
CMOS 5V tol
4
5
G3
G4
I/O
Control I/Os. These bi-directional signals control communication
between the PDI1394P23 and the LLC. Bus holders are built into
these terminals.
D0–D7
CMOS 5V tol
6, 7, 8,
9, 10,
11, 12,
13
H3, H4,
E4, H5,
F4, G5,
F5, H6
I/O
Data I/Os. These are bi-directional data signals between the
PDI1394P23 and the LLC. Bus holders are built into these terminals.
Unused Dn pins should be pulled to ground through 10 k
resistors.
DGND
Supply
17, 18,
63, 64
G7, H8,
G8, G1,
G2
—
Digital circuit ground terminals. These terminals should be tied together
to the low impedance circuit board ground plane.
DV
DD
Supply
25, 26,
61, 62
D8, E6,
F1, F2
—
Digital circuit power terminals. A combination of high frequency
decoupling capacitors near each side of the IC package are suggested,
such as paralleled 0.1
μ
F and 0.001
μ
F. These supply terminals are
separated from PLLV
and AV
internal to the device to provide noise
isolation. They should be tied at a low impedance point on the circuit
board.
ISO
CMOS
23
E8
I
Link interface isolation control input. This terminal controls the operation
of output differentiation logic on the CTL and D terminals. If an optional
isolation barrier of the type described in Annex J of IEEE Std 1394–1995
is implemented between the PDI1394P23 and LLC, the ISO terminal
should be tied low to enable the differentiation logic. If no isolation barrier
is implemented (direct connection), or bus holder isolation is
implemented, the ISO terminal should be tied high to disable the
differentiation logic.
LPS
CMOS 5V tol
15
H7
I
Link Power Status input. This terminal is used to monitor the
active/power status of the link layer controller and to control the state of
the PHY-LLC interface. This terminal should be either connected to the
LPS output of the LLC, or if no LPS terminal is available on the LLC the
LPS terminal can be connected to the V
DD
supplying the LLC through a
10 k
resistor. A pulsed signal should be used when an isolation barrier
exists between the LLC and PHY. (See Figure 8)
The LPS input is considered inactive if it is sampled low by the PHY for
more than 2.6
μ
s (128 SYSCLK cycles), and is considered active
otherwise (i.e., asserted steady high or an oscillating signal with a low
time less than 2.6
μ
s). The LPS input must be high for at least 21 ns in
order to be guaranteed to be observed as high by the PHY.
When the PDI1394P23 detects that LPS is inactive, it will place the
PHY-LLC interface into a low-power reset state. In the reset state, the
CTL and D outputs are held in the logic zero state and the LREQ input is
ignored; however, the SYSCLK output remains active. If the LPS input
remains low for more than 26
μ
s (1280 SYSCLK cycles), the PHY-LLC
interface is put into a low-power disabled state in which the SYSCLK
output is also held inactive. The PHY-LLC interface is placed into the
disabled state upon hardware reset.
The LLC is considered active only if both the LPS input is active and the
LCtrl register bit is set to 1, and is considered inactive if either the LPS
input is inactive or the LCtrl register bit is cleared to 0.
LREQ
CMOS 5V tol
1
H1
I
LLC Request input. The LLC uses this input to initiate a service request
to the PDI1394P23. Bus holder is built into this terminal.
NC
No connect
16, 54,
55
—
—
These pins are not internally connected and consequently are “don’t
cares”.
Other vendors’ pin compatible chips may require
connections and external circuitry on these pins.
PC0
PC1
PC2
CMOS 5V tol
20
21
22
F7
E7
F8
I
Power Class programming inputs. On hardware reset, these inputs set
the default value of the power class indicated during self-ID.
Programming is done by tying the terminals high or low. Refer to
Table 21 for encoding.
PD
CMOS 5V tol
14
G6
I
Power Down input. A logic high on this terminal turns off all internal
circuitry except the cable-active monitor circuits which control the CNA
output. For more information, refer to Section 17.2
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相關(guān)代理商/技術(shù)參數(shù)
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PDI1394P11 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3-port physical layer interface
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PDI1394P11BD 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3-port physical layer interface
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