參數(shù)資料
型號(hào)： PDI1394L41BE
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8358 PBGA ENCRP NO-PB
中文描述： 1 CHANNEL(S), 400M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： PLASTIC, QFP-144
文件頁(yè)數(shù)： 17/42頁(yè)
文件大?。?/td> 233K
代理商： PDI1394L41BE
Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2001 Sep 06
17
The Port Status page provides access to configuration and status information for each of the ports. The port is selected by writing 0 to the
Page_Select field and the desired port number to the Port_Select field in base register 7. The configuration of the port status page registers is
shown in Table 3 and corresponding field descriptions given in Table 4. If the selected port is unimplemented, all registers in the port status page
are read as 0.
Table 3. Page 0 (Port Status) Register Configuration
ADDRESS
BIT POSITION
3
0
1
2
4
5
6
7
1000
1001
1010
1011
1100
1101
1110
1111
AStat
BStat
Ch
Fault
Con
Bias
Dis
Peer_Speed
PIE
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 4. Page 0 (Port Status) Register Field Descriptions
FIELD
SIZE
2
TYPE
Rd
DESCRIPTION
AStat
TPA line state. This field indicates the TPA line state of the selected port, encoded as follows:
Code
Arb Value
11
Z
01
1
10
0
00
invalid
BStat
2
Rd
TPB line state. This field indicates the TPB line state of the selected port. This field has the same
encoding as the ASTAT field.
Child/parent status. A 1 indicates that the selected port is a child port. A 0 indicates that the selected
port is the parent port. A disconnected, disabled, or suspended port is reported as a child port. The Ch
bit is invalid after a bus-reset until tree-ID has completed.
Ch
1
Rd
Con
1
Rd
Debounced port connection status. This bit indicates that the selected port is connected. The
connection must be stable for the debounce time of 330ms–350ms for the Con bit to be set to 1. The
Con bit is reset to 0 by hardware reset and is unaffected by bus reset.
NOTE:
The Con bit indicates that the port is physically connected to a peer PHY, but the port is not
necessarily active.
Debounced incoming cable bias status. A 1 indicates that the selected port is detecting incoming cable
bias. The incoming cable bias must be stable for the debounce time of 41.6
μ
s–52
μ
s for the Bias bit to
be set to 1.
Bias
1
Rd
Dis
1
Rd/Wr
Port disabled control. If 1, the selected port is disabled. The Dis bit is reset to 0 by hardware reset (all
ports are enabled for normal operation following hardware reset). The Dis bit is not affected by bus
reset.
Peer_Speed
3
Rd
Port peer speed. This field indicates the highest speed capability of the peer PHY connected to the
selected port, encoded as follows:
Code
Peer Speed
000
S100
001
S200
010
S400
011–111
invalid
The Peer_Speed field is invalid after a bus reset until self-ID has completed.
NOTE:
Peer speed codes higher than 010b (S400) are defined in P1394a. However, the PDI1394P23
is only capable of detecting peer speeds up to S400.
PIE
1
Rd/Wr
Port event interrupt enable. When set to 1, a port event on the selected port will set the port event
interrupt (PEI) bit and notify the link. This bit is reset to 0 by a hardware reset, and is unaffected by
bus-reset.
Fault
1
Rd/Wr
Fault. This bit indicates that a resume-fault or suspend-fault has occurred on the selected port, and that
the port is in the suspended state. A resume-fault occurs when a resuming port fails to detect incoming
cable bias from its attached peer. A suspend-fault occurs when a suspending port continues to detect
incoming cable bias from its attached peer. Writing 1 to this bit clears the fault bit to 0. This bit is reset to
0 by hardware reset and is unaffected by bus reset.
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