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參數(shù)資料
| 型號： | PCM1737E |
| 英文描述： | 24-Bit, 192kHz Sampling Enhanced Multi-Level, Delta-Sigma, Audio DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 24位192kHz采樣增強(qiáng)的多級，Δ-Σ，音頻數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 26/27頁 |
| 文件大?。?/td> | 180K |
| 代理商： | PCM1737E |
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8
PCM1737
FIGURE 1. System Clock Input Timing.
SYSTEM CLOCK AND RESET
FUNCTIONS
SYSTEM CLOCK INPUT
The PCM1737 requires a system clock for operating the
digital interpolation filters and multi-level delta-sigma modu-
lators. The system clock is applied at the SCLK input (pin 5).
Table I shows examples of system clock frequencies for
common audio sampling rates.
Figure 1 shows the timing requirements for the system clock
input. For optimal performance, it is important to use a clock
source with low phase jitter and noise. Burr-Brown’s
PLL1700 multi-clock generator is an excellent choice for
providing the PCM1737 system clock.
SYSTEM CLOCK OUTPUT
A buffered version of system clock input is available at the
CLKO output (pin 4). CLKO can operate at either full
(fSCLK) or half (fSCLK/2) rate. The CLKO output frequency
may be programmed using the CLKD bit of Control Register
20. The CLKO output pin can also be enabled or disabled
using the CLKE bit of Control Register 20. The default is
CLKO enabled.
SAMPLING FREQUENCY
(fS)
128fS
192fS
256fS
384fS
512fS
768fS
16kHz
—
4.0960
6.1440
8.1920
12.2880
32kHz
—
8.1920
12.2880
16.3840
24.5760
44.1kHz
—
11.2896
16.9344
22.5792
33.8688
48kHz
—
12.2880
18.4320
24.5760
36.8640
88.2kHz
—
22.5792
33.8688
45.1584
See Note 1
96kHz
12.2880
18.4320
24.5760
36.8640
49.1520
See Note 1
176.4kHz
22.5792
33.8688
See Note 2
192
24.5760
36.8640
See Note 2
NOTE: (1) The 768fS system clock rate is not supported for fS > 64kHz. (2) This system clock rate is not supported for the given sampling frequency.
TABLE I. System Clock Rates for Common Audio Sampling Frequencies.
SYSTEM CLOCK FREQUENCY (fSCLK)
(MHz)
POWER-ON AND EXTERNAL RESET FUNCTIONS
The PCM1737 includes a power-on reset function. Figure 2
shows the operation of this function. The system clock input
at SCLK should be active for at least one clock period prior
to VDD = 2.0V. With the system clock active and VDD >
2.0V, the power-on reset function will be enabled. The
initialization sequence requires 1024 system clocks from the
time VDD > 2.0V. After the initialization period, the PCM1737
will be set to its reset default state, as described in the Mode
Control Register section of this data sheet.
The PCM1737 also includes an external reset capability
using the RSTB input (pin 22). This allows an external
controller or master reset circuit to force the PCM1737 to
initialize to its reset default state.
Figure 3 shows the external reset operation and timing. The
RSTB pin is set to logic ‘0’ for a minimum of 20ns. The
RSTB pin is then set to a logic “1” state, which starts the
initialization sequence which lasts for 1024 system clock
periods. After the initialization sequence is complete, the
PCM1737 will be set to its reset default state, as described
in the Mode Control Register section of this data sheet.
t
SCLKH
t
SCLKL
f
SCLK
System Clock Pulse Width High t
SCLKH
: 7ns min
System Clock Pulse Width Low t
SCLKL
: 7ns min
2.0V
0.8V
“H”
“L”
SCLK
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| PCM1737E-1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| PCM1738 | 制造商:BB 制造商全稱:BB 功能描述:24-Bit, 192kHz Sampling, Advanced Segment, Audio-Stereo DIGITAL-TO-ANALOG CONVERTER |
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